Clock recovery system for high speed small amplitude data stream

Details Clock recovery system for high speed small amplitude data stream Clock recovery system for high speed small amplitude data stream

1997-05-09

1999-11-09

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375355, H04L 700

Patent

active

059828340

ABSTRACT:
A clock recovery system that allows recovery of a clock signal from a high speed, potentially small amplitude data stream. The invention uses a normally avoided property of a non-linear oscillator in the clock recovery system in order to lock the oscillator in phase to an incoming signal. This property relates a characteristic of an oscillator that an oscillator amplifies noise near its inherent frequency; and if the noise is large enough, the oscillator squelches the inherent oscillator frequency signal and outputs a signal locked in frequency and phase to the noise. The clock recovery system comprises a processing circuit, an oscillator, and a control circuit. The processing circuit processes an input data stream to generate a current signal as a first control signal based on data transitions in the input data stream. The first control signal is a "noise signal" to the oscillator. The control circuit outputs a voltage control signal as a second signal to the oscillator based on a difference between an output fed back from the oscillator and a reference frequency signal matching the frequency of the input data stream within a predetermined tolerance range. The second control signal controls the oscillator so that the frequency of the oscillator output is substantially equal to that of the input data stream. Therefore, according to the invention, the oscillator is controlled by the first control signal such that the oscillator output is phase-locked and thus also frequency-locked to the input data stream.

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Behzad Razavi, "A2.5-Gb/s 15-mW Clock Recovery Circuit", Apr. 1997, IEEE Journal of Solid-State Circuits, vol. 31 No. 4.
Charles R. Hogge, Jr., "A Self Correcting Clock Recovery Circuit", Dec. 1985, Journal of Lightwave Technology, vol. LT-3 No. 6.
John F. Ewen et al. Single-Chip 1062Mbund CMOS Transceiver for Serial Data Communication, /95 IEEE International Solid-State Circuits Conference.

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