Clock recovery stabilization method and circuit in a receiver of

Details Clock recovery stabilization method and circuit in a receiver of Clock recovery stabilization method and circuit in a receiver of

1993-02-25

1994-07-12

Cangialosi, Salvatore

Pulse or digital communications

Repeaters

Testing

H04L 2730

Patent

active

053295463

ABSTRACT:
A process and circuit for down-converting a spread spectrum signal by first and second local oscillating signals, amplifying the down-converted signal, separating the amplified signal into intermediate base band signals of I and Q channels, and demodulating the intermediate base band signals in a receiver of a code division multiple access/direct sequence system. The amplified signal is squared to provide an intermediate frequency signal of 2f.sub.IF, which is then band pass filtered. The filtered signal is limiting-amplified to be maintained at a given level. A deviation under 1 dB of an input level is automatically adjusted in order to supplement an input dynamic range of the limiting-amplified signal, and the adjusted signal is divided to produce and intermediate frequency signal having a frequency of f.sub.IF. Moreover, a clock signal is recovered by the limiting-amplification of an oscillation signal generated in response to a phase difference obtained by comparing the intermediate frequency signal with a feedback signal of a recovery clock. The feedback signal is derived from the clock signal by dividing the clock signal after amplification. The clock signal is further divided and supplied as a stable carrier signal to a phase shifter via a band pass filter and amplifier. The two phase shifted carrier signals are mixed with the amplified signal in order to separate the amplified signal into the intermediate base band signals of the I and Q channels.

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