Clock recovery for multiple frequency input data

Details Clock recovery for multiple frequency input data Clock recovery for multiple frequency input data

1998-05-28

2001-05-22

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C331S025000

Reexamination Certificate

active

06236697

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data communication circuits and methods, and more specifically to circuits and methods for receiving digital data.
BACKGROUND OF THE INVENTION
Digital data is commonly transmitted and received between different data processing systems via electronic signals. Many data transmission formats include a clock that is separately transmitted with the data. Other data transmission formats are self-clocking, because every clock period includes a signal transition. Many other types of data transmissions are not self-clocking because they encode data as a series of high and low pulses of varying duration. Consecutive high or low pulses do not produce a transition between the pulses, so that pulses of varying duration are produced.
In order to recover a clock from an input signal, it is known to provide clock recovery circuits and methods. See for example, U.S. Pat. No. 5,671,258 to Burns et al. entitled “Clock Recovery Circuit and Receiver Using Same”, and U.S. Pat. No. 5,689,692 to MacTaggart et al. entitled “Method and Apparatus for Decoding an Encoded NRZ Signal”.
Clock recovery can become complicated for variable frequency input data. For example, when using Asynchronous Transfer Mode (ATM) data transmission formats, data may be transmitted at either 32 megabits per second (Mbps) or 64 Mbps. Since ATM data may include an extra bit for every four consecutive zero bits, these transmission rates generally correspond to effective data rates of about 25 Mbps and about 50 Mbps respectively.
Clock recovery circuits and methods often include a phase locked loop to lock onto a clock frequency. As is well known to those having skill in the art, a phase locked loop generally includes a reference clock or oscillator. Accordingly, when recovering clock signals from multiple frequency input data, multiple phase locked loops and multiple reference clocks may be provided. In an integrated circuit with multiple input data ports, the proliferation of multiple phase locked loops and multiple reference clocks may unduly complicate the integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide circuits and methods that can recover a clock from an input data signal.
It is another object of the invention to provide clock recovery circuits and methods that can recover a clock from an input signal of variable frequency.
It is yet another object of the present invention to provide multiple frequency input signal clock recovery circuits and methods that do not require separate phase locked loops and reference oscillators for each of the multiple frequencies.
These and other objects are provided according to the present invention by clock recovery circuits and methods that include a first phase locked loop that generates a control signal in response to a reference clock. A pulse generating and delaying circuit is responsive to the input data signal to generate from the input data signal pulses of predetermined width that are delayed by a predetermined delay. A second phase locked loop is responsive to the control signal, to the pulse generating and delaying circuit and to a mode signal, to generate a clock signal from the input data signal. Accordingly, only the first phase locked loop need include a reference clock. Cost and/or complexity can therefore be reduced.
Moreover, in an integrated circuit that includes multiple data ports, only the pulse generating and delaying circuit and the second phase locked loop may need to be duplicated for each data port, to allow each data port to operate at a frequency that is independent of the other data ports. A common first phase locked loop, including a common reference clock, may provide a common control signal to all data ports. By using a common first phase locked loop, greater frequency uniformity of the clock that is generated for each of the ports may be obtained. Moreover, the integrated circuit area that is consumed by the clock recovery circuits may be reduced.
Clock recovery circuits and methods according to the present invention, recover a clock from an input signal that is received at a first frequency or at a second frequency, in response to a mode signal that indicates whether the first or second frequency is received. A first phase locked loop generates a control signal in response to a reference clock. A pulse generating and delaying circuit is responsive to the input data signal and to the mode signal, to generate from the input data signal pulses of predetermined width that are delayed by a predetermined delay. At least one of the predetermined width and the predetermined delay is a function of the mode signal. A second phase locked loop is responsive to the control signal and to the pulse generating circuit, to generate a clock signal from the input data signal.
The second phase locked loop preferably includes a phase detector that is responsive to the pulse generating and delaying circuit, and a controlled oscillator that is responsive to the phase detector and to the first phase locked loop. A variable frequency divider is responsive to the controlled oscillator and to the mode signal, to divide the output of the controlled oscillator by a first value or by a second value in response to the mode signal. The phase detector is also responsive to the variable frequency divider. The pulse generating and delaying circuit is also preferably responsive to the control signal.
The pulse generating and delaying circuit may include a pulse generator and a variable delay circuit, both of which are responsive to the mode signal. More specifically, the pulse generator is responsive to the input data signal and to the mode signal, to generate a pulse of pulse width that is a function of the mode signal, for each transition of the input data signal. A variable delay circuit is responsive to the pulse generator and to the mode signal, to delay the pulses by a delay that is a function of the mode signal. The phase detector is responsive to the variable delay circuit.
According to another aspect of the invention, only the variable delay circuit need be responsive to the mode signal. Accordingly, the pulse generating and delaying circuit can include a pulse generator that is responsive to the input data signal, to generate a pulse of fixed pulse width for each transition of the input data signal. A variable delay circuit is responsive to the pulse generator and to the mode signal to delay the pulses by a delay that is a function of the mode signal. The phase detector is responsive to the variable delay circuit.
In the above aspects, a gate may also be included that is responsive to the pulse generator and to the variable frequency divider, to gate the variable frequency divider by the pulse. The phase detector is responsive to the variable divider as gated by the gate.
Clock recovery circuits and methods according to the invention may be used in a data receiver including a clocked flip-flop having a data input and a clock input. The data input is responsive to the input data signal and the clock input is responsive to the clock signal that is generated by the clock recovery circuits or methods. The data signal is thereby clocked. Accordingly, multiple frequency input data may be clocked using two phase locked loops and a pulse generating and delaying circuit.
Only one reference clock need be used, and this reference clock need not be replicated for multiple data ports that operate at multiple frequencies. Low cost and/or high performance clock recovery circuits and methods may thereby be provided.


REFERENCES:
patent: Re. 34317 (1993-07-01), Ikeda
patent: 3993868 (1976-11-01), Balcewicz
patent: 4912566 (1990-03-01), Tasaka
patent: 5671258 (1997-09-01), Burns et al.
patent: 5689692 (1997-11-01), MacTaggart et al.
patent: 6094236 (2000-07-01), Abe et al.

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