Clock recovery circuit for high-speed data signal transmission

Details Clock recovery circuit for high-speed data signal transmission Clock recovery circuit for high-speed data signal transmission

2007-04-10

2007-04-10

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S500000, C398S155000

Reexamination Certificate

active

10405243

ABSTRACT:
A clock recovery circuit has a phase comparator circuit, a phase adjusting circuit, and a duty cycle correction circuit. The phase comparator circuit carries out phase comparison between an input signal and an output signal, and outputs a phase control signal proportional to a phase difference between the input signal and the output signal. The phase adjusting circuit receives the phase control signal from the phase comparator circuit, adjusts the phase of the input signal, and produces the output signal, and the duty cycle correction circuit receives the output signal from the phase adjusting circuit, and corrects the duty cycle of the output signal.

REFERENCES:
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patent: 6466071 (2002-10-01), Kim et al.
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patent: 2001-144590 (2001-05-01), None
Ogawa et al., “A 50% Duty Control Circuit for PLL Output”, ECT-01-72, pp. 15-19 (2001).
Lee et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM”, Solid State Circuits, J. of IEEE, vol. 29, Issue 12, pp. 1491-1496 (1994).

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