Clock recovery circuit and transmitter-receiver therewith

Details Clock recovery circuit and transmitter-receiver therewith Clock recovery circuit and transmitter-receiver therewith

2000-09-26

2004-08-03

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S327000, C327S148000, C327S157000

Reexamination Certificate

active

06771729

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns a clock recovery circuit with a voltage-controlled oscillator, which generates a clock that continuously maintains a fixed phase to each piece of input data, and a transmitter-receiver therewith.
2. Description of the Related Arts
When data is exchanged in data communication such as that between mobile telecommunication devices, data and a clock used for processing that data are generally necessary. In that case, for example, assuming that data is being exchanged between area A and area B, naturally, the exchange of data and clock between A and B is necessary. But in recent years, because the amount of data being exchanged has greatly increased and transfer rates have become increasingly fast, it is desirable to have as few signals as possible.
Which lead to the question now of whether data-only can just be sent instead of before where once both data and clock needed to be sent together. It is here that a clock recovery circuit is applicable.
A clock recovery circuit can come up with a clock synchronized to the data based solely on a data-only signal, and to give an example, if the data sent comes in at 500 Mbps, the clock recovery circuit sets up a 500 MHz clock based on that data. At this time, this clock is completely synchronized to the data, and generated with a constant phase to the data.
The reason the clock phase is aligned with the data comes from the fact that the clock generated by the clock recovery circuit is necessary for processing data, and a series of data processing, such as reading out data, is preformed in sync with the timing of the clock. To explain it more specifically, in a process that has been set to read-in data timed with the rising edge of the clock signal, for example, if the read-out is performed with the same timing, the danger of an erroneous (misaligned) read-out virtually disappears. However, if the timing of the data being read-in is inconsistent or random, it is possible that data that has already been read-in might be read-in again. Also, even if the read-out timing has been made constant, when the data read-out position (which is designated by the clock) falls within the transient region of the data, the receiving-side might have difficulty recognizing which data has been read-in before and after the transient region of data. In order to solve this problem, it is necessary to synchronize each of the clock phases to a constant position of each piece of data.
By using the clock recovery circuit in this manner, since the clock for data processing has been generated solely from only the data that has been sent, data communication between A and B can take place without the extra step of sending a data processing clock.
However, the following problems have arisen with conventional technology and are described below.
Conventionally, a wideband VCO (voltage-controlled oscillator) was needed when planning the layout of a wideband clock recovery circuit. However, with regard to manufacturing process variations, environmental variations and the like, it is exceedingly difficult to make a VCO that can guarantee a wide range of oscillations.
In order to design a clock recovery circuit, it is normally necessary to take into consideration beforehand the manufacturing process variations, environmental variations, and the like. These variations cause the occurrence of different guaranteed oscillation ranges of a VCO. For example, assume the information below is obtained as a result of planning.
Good conditions: VCO oscillates within the range of 200 MHz to 600 MHz
Normal conditions: VCO oscillates within the range of 150 MHz to 600 MHz
Poor conditions: VCO oscillates within the range of 100 MHz to 600 MHz In this case, the oscillation range guaranteed by all conditions is 200 MHz (the lowest oscillation frequency during “good conditions”) to 400 MHz (the highest oscillation frequency during “poor conditions”). In this manner, designing a clock recovery circuit, while keeping in mind the changes involved in semiconductor manufacturing processes, causes an occurrence of unavoidable problems making designing a widened oscillation range quite difficult to accomplish.
SUMMARY OF THE INVENTION
Accordingly, the present invention takes the above problems into consideration, with its objective being to provide a wideband clock recovery circuit depending on a frequency-dividing formula without a wideband VCO, and also to provide a transmitter-receiver therewith. The key point to attain the above objective is to control the problematic changes in the loop gain that are caused by the changes in the frequency-division factor. With this control, the clock recovery circuit, according to the present invention, can maintain the characteristic stability in all of the various frequencies.
According to an aspect of the present invention, a clock recovery circuit, which generates a recovery clock signal (CLOCK) that continuously maintains a fixed phase to an input data signal (DATA), is provided and is comprised of a frequency-divider (
2
), which frequency-divides a first clock signal (clock
1
) by a selectable frequency-division factor into a resulting second clock signal (clock
2
); and a charge pump (
9
), which outputs a selectable amount of VCO control electric current, wherein said selectable amount of VCO control electric current is selected in conformity with said selectable frequency-division factor. An example of this clock recovery circuit is shown in FIG.
1
.
According to an aspect of the present invention, a transmitter-receiver is provided and is comprised of a demodulator (
102
), which demodulates an input data signal; and a recovery clock/data recovery circuit (
101
), which generates a recovery clock (CLOCK) and recovered data, with said recovery clock (CLOCK) continuously maintaining a fixed phase to modulated input data signal (DATA). The recovery clock/data recovery circuit (
101
) is comprised of a frequency-divider (
2
), which frequency-divides a first clock signal (clock
1
) by a selectable frequency-division factor into a resulting second clock signal (clock
2
); and a charge pump (
9
), which outputs a selectable amount of VCO control electric current, wherein said selectable amount of VCO control electric current is selected in conformity with said selectable frequency-division factor. An example of this transmitter-receiver is shown in FIGS.
5
and
6
.


REFERENCES:
patent: 5220294 (1993-06-01), Ichikawa
patent: 5950115 (1999-09-01), Momtaz et al.
patent: 5952890 (1999-09-01), Fallisgaard et al.
patent: 6218876 (2001-04-01), Sung et al.
patent: 05-090962 (1993-04-01), None
patent: 06-029836 (1994-02-01), None
patent: 06-045922 (1994-02-01), None
patent: 07-079158 (1995-03-01), None
patent: 2001-016102 (2001-01-01), None
patent: 2001-016103 (2001-01-01), None

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