Clock recovery circuit and phase detecting method therefor

Details Clock recovery circuit and phase detecting method therefor Clock recovery circuit and phase detecting method therefor

2000-06-15

2004-05-25

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S372000, C370S503000

Reexamination Certificate

active

06741668

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock recovery circuit being of high speed and low jitter in which a clock signal can be recovered by a clock signal of 1/&pgr; frequency of the data rate “n” bps (bit per second) of inputted serial random data and a phase detecting method which can realize this clock recovery circuit.
Description of the Related Art
FIG. 1
is a block diagram showing a conventional clock recovery circuit. As shown in
FIG. 1
, the conventional clock recovery circuit consists of a phase detector (PD)
101
which receives inputted serial random data having the data rate of “f” bps and compares the phase of a clock signal oscillating about “f” Hz generated by a voltage controlled oscillator (VCO)
104
with the phase of the received inputted serial random data, a charge pump (CP)
102
which receives up pulses and down pulses showing the result of the phase comparison at the PD
101
and supplies charge/discharge current in response to the up and down pulses to a loop filter (LPF)
103
, the LPF
103
which removes unnecessary noise included in the output from the PD
101
, and the VCO
104
which makes the oscillating frequency change in response to the charge/discharge current that is outputted from the CP
102
and is removed the noise at the LPF
103
.
Generally, a Hogge type phase detector is used for comparing the phase of the inputted serial random data having the data rate of “f” bps with the phase of the clock signal of “f” Hz.
FIG. 2
is a block diagram showing the Hogge type phase detector used for the conventional clock recovery circuit and a timing chart of output signals from the functions shown in FIG.
1
. Referring to
FIG. 2
, structure and operation of the Hogge type phase detector are explained. The timing chart in
FIG. 2
shows signal output timing of each function at the time when the clock signal lagged and led for the inputted serial random data and is synchronized with the inputted serial random data.
As shown in
FIG. 2
, the Hogge type phase detector consists of a delayed flip flop (F/F)
105
to which the serial random data and a clock signal (hereinafter referred to as CLK) A from a VCO (not shown) are inputted, an inverter
110
which inverts the CLK A, a delayed flip flop (F/F)
106
to which the output from the F/F
105
and a CLK B inverted the CLK A at the inverter
110
are inputted, an exclusive-or (EX-OR) circuit
107
to which the serial random data and the output from the F/F
105
are inputted, an EX-OR circuit
108
to which the outputs from the F/Fs
105
and
106
are inputted, and an inverter
109
which inverts the output from the EX-OR circuit
107
.
At the Hogge type phase detector mentioned above, the EX-OR circuit
107
applies EX-OR for the waveform of the inputted serial random data and the waveform of the output from the F/F
105
which the CLK A is applied to the serial random data received at the F/F
105
. The output from the EX-OR circuit
107
is inverted at the inverter
109
and outputted, this output is named as UP pulses (the waveform of the EX-OR
107
in FIG.
2
).
And the EX-OR circuit
108
applies EX-OR for the waveform of the output from the F/F
105
and the waveform of the output from the F/F
106
which the CLK B is applied to the output from the F/F
105
at the F/F
106
. The output from the EX-OR circuit
108
is named as DOWN pulses (the waveform of the EX-OR
108
in FIG.
2
).
Referring to the waveforms of pulses shown in
FIG. 2
, the mentioned above UP and DOWN pulses are explained in cases that the phase of the clock signal lagged and led for the inputted serial random data, and is synchronized with the inputted serial random data. In this, the synchronized state is that the rising edge of the CLK A is at the center of the data.
As shown in
FIG. 2
, the width of the DOWN pulses is always constant at the time when the phase of the clock signal lagged or led for the inputted serial random data and are synchronized with the inputted serial random data. And the width of the DOWN pulses is ½ of the inputted serial random data.
On the other hand, the width of the UP pulses varies. That is, in case that the phase of the clock signal lagged for the inputted serial random data, the width is wide, in case that the phase of the clock signal is synchronized with inputted serial random data, the width is the same as the DOWN pulse, and in case that the phase of the clock signal led for the inputted serial random data, the width is narrow. In
FIG. 2
, the UP pulse is shown as a convex shape to the downward direction, and &thgr;e shows the phase difference between the clock signal and the inputted serial random data.
The net difference between the widths of the UP and DOWN pluses is used for a charging/discharging current to the LPF
103
through the CP
102
. That is, when the phase of the clock signal lagged, the net width of the UP pulse becomes large, when the phase of the clock signal led, the net width of the DOWN pulse becomes large. And when the phase of the clock signal is synchronized with the phase of the inputted serial random data, the net difference between the widths of the UP and DOWN pulses becomes “0”.
However, at the Hogge type phase detector mentioned above, as shown in
FIG. 2
, even when the phase of the clock signal is synchronized with the inputted serial random data, a large current flows through the CP
102
in response to the UP and DOWN pulses, therefore, there is a problem that the jitter characteristic at the synchronized state is deteriorated.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a clock recovery circuit and a phase detecting method used for this circuit, in which a current flowing through a charge pump is made to zero at the time when the clock recovery circuit is synchronized, and the jitter characteristic is improved at the time when the clock recovery circuit is synchronized. And further another object of the present invention is to provide a clock recovery circuit and a phase detecting method used for this circuit which can perform high speed clock recovery not controlled by any oscillating frequency of a voltage controlled oscillator.
According to a first aspect of the present invention, for achieving the objects mentioned above, there is provided a clock recovery circuit. The clock recovery circuit provides multi phase clock signal generating means which generates a reference clock signal whose frequency is controlled to be about f/2 Hz for inputted serial random data whose data rate is “f” bit per second (bps), and also generates a plurality of clock pulses whose phases are different from the reference clock signal, edge detecting means for detecting rising edges and falling edges of the inputted serial random data, detected edge selecting means which selects whether the detected edges of the inputted serial random data are compared their phases with rising edges or falling edges of the reference clock signal, and outputs first edge pulses synchronized with edges which are judged to be compared their phases with the rising edges of the reference clock signal and second edge pulses synchronized with edges which are judged to be compared their phases with the falling edges of the reference clock signal, first edge position correction for comparing edges means which corrects so that the frequency of a first clock pulse becomes equal to the frequency of the first edge pulses by selecting only edges of the first clock pulses which perform phase comparison with the first edge pulses in the edges of the first clock pulses which are used at the phase comparison with the rising edges of the reference clock signal, and also makes edges of the first edge pulses lag by phase difference between the reference clock signal and the first clock pulse, second edge position correction for comparing edges means which corrects so that the frequency of a second clock pulse becomes equal to the frequency of the second edge pulses by selecting only edges of the second clock pulses which perform p

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