Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

1994-11-30

1998-05-26

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

370505, H04L 700, H04L 2536, H04L 2540

Patent

active

057578729

ABSTRACT:
A clock recovery circuit is coupled to an elastic storage circuit such as a FIFO circuit. More specifically, a first input of the elastic storage circuit is electrically connected to an output of the clock recovery circuit. A second input for accepts a data signal representing an input data stream from a communications medium. A third input accepts a local clock signal. The resultant circuit may be used in receiver's for communications systems to help alleviate the problems of frequency mismatch and jitter.

REFERENCES:
patent: 4392234 (1983-07-01), Maruta
patent: 4393279 (1983-07-01), Cochrane et al.
patent: 4823365 (1989-04-01), Loginov
patent: 4928275 (1990-05-01), Moore et al.
patent: 5077761 (1991-12-01), Tokunaga
patent: 5237290 (1993-08-01), Banu et al.
patent: 5255293 (1993-10-01), Archer et al.
patent: 5272728 (1993-12-01), Ogawa
patent: 5274681 (1993-12-01), Yamada et al.
patent: 5402425 (1995-03-01), Bladh
Introduction to VLSI Systems, Addison-Wesley Series in Computer Science, Consulting Editor, Michael A. Harrison, 1980,pp. 258-260.

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