Clock recovery circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S373000, C375S371000, C375S354000

Reexamination Certificate

active

08054930

ABSTRACT:
A circuit is provided for clock recovery. The circuit includes a reference extraction unit for extracting from a datastream time references defining a reference time base, and a digital Phase Locked Loop including a first programmable counter in the guise of a digitally controlled oscillator for overseeing an output time base, a second programmable counter in the guise of a loop divider for overseeing a loop time base, and a dedicated processor capable of executing a program including a first software module in the guise of a phase comparator for comparing values of the loop and reference time bases and generating a loop error, and a second software module in the guise of a loop filter for producing an adaptation value of an increment value of the first programmable counter from the loop error. Also provided are a user terminal and a method for clock recovery.

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patent: 0 836 282 (1998-04-01), None
patent: WO 01/22736 (2001-03-01), None
French Preliminary Search Report dated Dec. 18, 2003 for French Application No. 0305565.

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