Clock recovery circuit

Details Clock recovery circuit Clock recovery circuit

2000-12-12

2002-05-21

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C331S025000, C327S156000

Reexamination Certificate

active

06393084

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a clock recovery circuit for reproducing a clock signal synchronized with an input signal quantized to a digital value from the input signal.
In a data reproducing apparatus for decoding a data signal recorded in a recording medium such as an optical disk and a magnetic disk, in order to identify a reproduction signal from the recording medium as data, it is necessary to recover a clock signal synchronized with this reproduction signal from the reproduction signal.
In general, a clock recovery circuit in a digital system includes a phase comparator, a loop filter, a D/A converter and a VFO (variable frequency oscillator). The VFO generates an oscillating clock signal of a variable frequency under control of an analog voltage. The phase comparator computes a digital value representing a phase error of the oscillating clock signal with respect to an input signal quantized to a digital value and outputs a phase error signal in a digital system as described, for example, in K. H. Mueller et al., “Timing Recovery in Digital Synchronous Data Receivers”, IEEE Transactions on Communications, Vol. COM-24, No. 5, pp. 516-531, May 1976. The loop filter is a circuit block for smoothing a digital output from the phase comparator and outputting the smoothed digital output. The D/A converter converts the digital output from the loop filter to an analog voltage so as to control generation of the oscillating clock signal so that the phase error is zero, and supplies the analog voltage to the VFO.
FIG. 17
shows an example of the configuration of a conventional loop filter. In
FIG. 17
, reference numeral
31
and
32
denote first and second constant multipliers, reference numeral
34
denotes an accumulator, and reference numeral
35
denotes an adder. The first constant multiplier
31
outputs a result obtained by multiplying a phase error signal E output from the phase comparator by a constant filter coefficient &agr;. The second constant multiplier
32
outputs a result obtained by multiplying the phase error signal E by a constant filter coefficient &bgr; (<&agr;). The accumulator
34
outputs a result obtained by accumulating outputs H from the second constant multiplier
32
, and includes an adder
91
and a latch
92
. The adder
35
adds an output G from the first constant multiplier
31
and an output Y from the accumulator
34
. A digital value representing the result of this addition, namely, a filter output Z, is supplied to the VFO via the D/A converter.
FIG. 18
shows an example of a waveform of each portion of the loop filter of
FIG. 17
when the clock recovery circuit is operated. A frequency pull-in operation is performed for a period during which a frequency error is contained in an oscillating clock signal of the VFO. When the frequency pull-in is completed, a phase pull-in operation is started. In the example of
FIG. 18
, a frequency pull-in is completed and a phase pull-in operation is started in cycle
7
, and the phase pull-in is completed in cycle
46
. In the frequency lock state around cycle
7
, E=14 (constant), and G=5, Y=1, and Z=6. The output G (=5) from the first multiplier
31
represents a frequency correction component. In the phase lock state after cycle
46
, E=0, and G=0, Y=4, and Z=4. In this case, the unit of these examples of the values is arbitrary.
According to the conventional loop filter shown in
FIG. 17
, during a period from the start of the phase pull-in operation to the completion of the phase pull-in, a main portion of the filter output Z (=G+Y) has to shift from the output G from the first multiplier
31
to the output Y from the accumulator
34
. In the specific example of
FIG. 18
, during this period, the output G from the first multiplier
31
changes from 5 to 0, whereas the output Y from the accumulator
34
changes 1 to 4. However, since the filter coefficient &bgr; is set to small for stable operation of the clock recovery circuit, the change of the output Y from the accumulator
34
is slow. Therefore, in the example of
FIG. 18
, the start of the phase pull-in operation to the completion of the pull-in takes as long a time as 39 clock cycles.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a clock recovery circuit that can achieve high-speed phase pull-in.
In order to achieve this object, a first clock recovery circuit of the present invention includes a loop filter including first and second multipliers for multiplying a digital output from a phase comparator by respective filter coefficients and outputting the results; a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; an enable-provided latch for outputting a constant value 0 for a period during which the control signal is not output, and after the control signal is output, storing the output from the first multiplier at the time when the control signal is output, and outputting the same; an accumulator for accumulating outputs from the second multiplier and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator as a filter output, wherein a phase pull-in operation is started using the stored value of the output from the first multiplier at the time of completion of the frequency pull-in.
According to the first clock recovery circuit, since the output from the enable-provided latch is 0 during the frequency pull-in operation, the sum of the output from the first multiplier and the output from the accumulator is the filter output as in the conventional example. However, when frequency pull-in is completed, and a frequency lock state is reached, the output from the first multiplier at the time of completion of the frequency pull-in is stored in the enable-provided latch. Thus, a phase pull-in operation is started in the state where a frequency correction component is stored collectively in the latch that is discrete from the accumulator. Then, during a phase pull-in operation, the sum of the output from the first multiplier, the output from the enable-provided latch, and the output from the accumulator is the filter output. Therefore, high speed phase pull-in can be attained.
A second clock recovery circuit includes a loop filter including a control signal generating portion for outputting a control signal at the time when completion of frequency pull-in is detected based on the digital output from the phase comparator; a multiplier for outputting a result obtained by multiplying the digital output from the phase comparator by a first filter coefficient for a period during which the control signal is not output, and after the control signal is output, multiplying the digital output from the phase comparator by a second filter coefficient; an enable-provided accumulator for accumulating a constant value 0 for a period during which the control signal is not output, and accumulating outputs from the multiplier after the control signal is output and outputting a result; and an adder for supplying a digital value representing a result of addition of the output from the multiplier and the output of the enable-provided accumulator as a filter output, wherein a phase pull-in operation is started using a stored value of the output from the multiplier at the time of completion of the frequency pull-in.
According to the second clock recovery circuit, since the output from the enable-provided accumulator is 0 during the frequency pull-in operation, the filter output depends only on the output from the multiplier having a first filter coefficient as the multiplier factor. When the frequency pull-in is completed and a frequency lock state is reached, the output from the multiplier at the time of completion of the frequency pull-in is sto

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