Clock processors in high-speed signal converter systems with...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C341S118000, C341S126000

Reexamination Certificate

active

07870415

ABSTRACT:
Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

REFERENCES:
patent: 5148113 (1992-09-01), Wight et al.
patent: 5608357 (1997-03-01), Ta et al.
patent: 5872810 (1999-02-01), Philips et al.
patent: 6804633 (2004-10-01), Nygaard, Jr.
patent: 7012956 (2006-03-01), Thomsen et al.
patent: 7099382 (2006-08-01), Aronson et al.
patent: 7130367 (2006-10-01), Fu et al.
patent: 7184509 (2007-02-01), Cho et al.
Farjad-Rad, Ramin, “A 0.3um CMOS 8-Gb/s 4-PAM Serial Link Transceiver”, IEEE Journal of Solid-State Physics, vol. 35, No. 5, May 2000, pp. 757-764s.
Bartolome, Eduardo, “Clocking high-speed data converters”, Analog and Mixed Signal Products— Analog Applications Journal, Jan. 2005, pp. 20-26.
King , Ian, “Capturing Data from Gigasample Analog-to-Digital Converters” Xcell Journal, Jan. 2006, pp. 5-9s.
Sidiropoulos, Stefanos, “A Semidigital Dual Delay-Locked Loop”, IEEE Journal of Solid-State Physics, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
“Digital Waveform Timing”, National Instruments Tutorial, Feb. 2006, pp. 1-5.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Clock processors in high-speed signal converter systems with... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock processors in high-speed signal converter systems with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock processors in high-speed signal converter systems with... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2645029

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.