Clock phase shifting method and apparatus

Details Clock phase shifting method and apparatus Clock phase shifting method and apparatus

1993-12-09

1996-10-01

Tse, Young T.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375373, 327152, 327153, 331 57, 370108, 3701053, H04L 7027

Patent

active

055616925

ABSTRACT:
A circuit for providing a phase controlled clock output includes a ring oscillator having a delay line for providing an internal clock signal whose period varies with on-chip variations due to temperature, voltage, and process. The circuit also includes a clock phase select circuit having a counter and divider for determining the number of delays in one external clock period and an input for a phase select value. A delay line having delay elements similar to those of the ring oscillator provides multiple delayed clock signals from the reference clock signal. A multiplexor having odd and even sides is used to select the desired clock signal in a glitchless manner. The phase controlled clock signal output is controlled by the phase select signal and is compensated for on-chip variations due to temperature, voltage, and process.

REFERENCES:
patent: 4677648 (1987-06-01), Zurflur
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5018169 (1991-05-01), Wong et al.
patent: 5077529 (1991-12-01), Ghoshal et al.
patent: 5220581 (1993-06-01), Ferraiolo et al.

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