Clock phase generator for controlling operation of a DRAM array

Details Clock phase generator for controlling operation of a DRAM array Clock phase generator for controlling operation of a DRAM array

2000-03-02

2000-11-14

Dinh, Son T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327270, 327271, H03H 1126

Patent

active

061475351

ABSTRACT:
A structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.

REFERENCES:
patent: 5615169 (1997-03-01), Leung
patent: 5708624 (1998-01-01), Leung
patent: 5778237 (1998-07-01), Yamanoto et al.
patent: 5829026 (1998-10-01), Leung et al.
patent: 6020773 (2000-02-01), Kan et al.
patent: 6052011 (2000-04-01), Dasgupta

Affiliated with

Also associated with

Rating

Clock phase generator for controlling operation of a DRAM array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock phase generator for controlling operation of a DRAM array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock phase generator for controlling operation of a DRAM array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2068682