Clock network for field programmable gate array

Details Clock network for field programmable gate array Clock network for field programmable gate array

1997-01-03

1999-04-06

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 93, 326 41, 327297, H03K 738, H03K 1900

Patent

active

058923705

ABSTRACT:
A clock network of a field programmable gate array has a first clock bus extending across the chip in a first dimension. A clock pad can be coupled to the first clock bus if the clock network is to be driven from the clock pad. An output of a selected logic cell can be coupled to the first clock bus if the clock network is to be driven from a logic cell. To increase speed of the clock network, the first clock bus is segmented (in one embodiment, collinearly extending segments can be selectively coupled together via selectively programmable antifuses) so that only a short piece of the first clock bus is used to couple either the pad or the logic cell to the clock network in high speed applications.

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