Clock multiplier and method of multiplying a clock

Details Clock multiplier and method of multiplying a clock Clock multiplier and method of multiplying a clock

2007-08-17

2009-12-22

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S116000, C327S119000, C327S156000, C327S160000

Reexamination Certificate

active

07636002

ABSTRACT:
A clock multiplier for multiplying an input clock by N includes a phase/frequency detector, a clock selector, and a voltage-controlled delay line. The phase/frequency detector generates a first control signal and a second control signal according to a frequency/phase difference between the input clock and a count signal indicating a signal that is generated by delaying the input clock N times. The clock selector selects one of the input clock and a feedback clock based on the input clock and the count signal. The voltage-controlled delay line adjusts a delay time of the selected signal according to a control voltage that is generated based on the first control signal and the second control signal, and outputs the feedback clock based on the adjusted signal. The clock multiplier operates without accumulating a frequency/phase difference between the input clock and the output clock when the multiplying ratio is increased.

REFERENCES:
patent: 6052034 (2000-04-01), Wang et al.
patent: 6064244 (2000-05-01), Wakayama et al.
patent: 6140854 (2000-10-01), Coddington et al.
patent: 6392456 (2002-05-01), Pyeon et al.
patent: 2001-136060 (2001-05-01), None
patent: 2002-232290 (2002-08-01), None
patent: 2003-121505 (2003-04-01), None

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