Clock monitor circuit and synchronous semiconductor memory...

Details Clock monitor circuit and synchronous semiconductor memory... Clock monitor circuit and synchronous semiconductor memory...

1999-06-01

2001-10-23

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S166000, C327S176000, C327S161000

Reexamination Certificate

active

06307412

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock monitor circuit and, more particularly to a clock monitor circuit and synchronous semiconductor memory device utilizing the clock monitor circuit for monitoring the presence of a clock signal irrespective of its period.
2. Description of the Prior Art
Generally, a clock monitor circuit is adapted to monitor whether an input clock signal is present in a device that is synchronously operated by the input clock signal. If an input clock signal is not detected, the device stops operating, thereby preventing unnecessary waste of electric power.
In this regard, U.S. Pat. No. 4,633,097 describes a clock monitor circuit that changes two charge storage nodes and allows output to maintain a logic high level when an input clocking signal is present and a logic low level when the clocking signal is not present. The circuit therein described comprises a CMOS transistor that monitors the presence of the clocking signal by charging a node. For this reason, one disadvantage in this clock monitor circuit is that circuit's output signal is delayed by its RC time constant. Moreover, the clock monitor circuit cannot be used in a system where the period of the clock signal is longer than the circuit's RC time constant.
In addition, U.S. Pat. No. 5,619,643 describes a clock monitor circuit that detects an error state in a clocking signal used in a microprocessor system. The clock monitor circuit determines whether a clocking signal is present or not by charging and discharging a capacitance. Accordingly, like the circuit described in U.S. Pat. No. 4,633,097, the circuit disclosed in U.S. Pat. No. 5,619,643 monitors the clock signal by applying an electric charge. Therefore, just like the circuit described in the '097 patent, the clock monitor circuit of the '643 patent has the disadvantage of not being able to be used in a system where the period of the clock signal is longer than the RC time constant of the circuit.
A conventional synchronous semiconductor memory device generally has two modes of operation. In an operation mode, operations arc synchronous with an externally input clock signal. In a standby mode, operations are stopped when the externally input clock signal is not present. However, because some circuits in the device operate irrespective of the clock signal, these circuits unnecessarily waste electric power during the standby mode.
To prevent this problem, conventional devices are provided with an additional power-down pin that stops all operations by applying a power-down signal when a user wants to utilize the standby mode in the device irrespective of the outside clock signal. However, providing an additional power down pin increases manufacturing costs.
Accordingly, a need remains for a clock monitor circuit that overcomes the problems associated with prior art clock monitor circuits.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems of prior art clock monitor circuits.
It is another object of the present invention to provide a clock monitor circuit that monitors the presence of a clock signal irrespective of its period.
It is further an object of the present invention to provide a synchronous semiconductor memory device having a clock monitor circuit that prevents unnecessary waste of electric power during a standby mode. The clock monitor circuit of the present invention includes a first delay and clock signal generating circuit for receiving a clock signal and generating a first internal clock signal, the first internal clock signal making a first transition a first predetermined time after the clock signal makes a corresponding first transition. A second delay and clock signal generating circuit receives an inverted clock signal and generates a second internal clock signal, the second internal clock signal making a second transition a second predetermined time after the clock signal makes a corresponding second transition. A first logic gate generates a stop signal by logically manipulating the first and second internal clock signals.
The first delay and clock generating circuit comprises a first delay circuit for generating a first delay pulse. The first delay pulse makes a first change in logic states a first delay time after the clock signal makes a corresponding first change in logic states and makes a second change in logic states a second delay time after the clock signal makes a corresponding second change in logic states. A second logic gate generates the first internal clock signal by logically manipulating the first delay pulse and the clock signal.
The first delay circuit includes a first plurality of serially connected inverters. The first plurality of serially connected inverters comprises a first predetermined number of first inverters each having a first pull-up transistor and a first pull-down transistor, each first pull-up transistor having a small size and each first pull-down transistor having a large size. Also comprising the first delay circuit is a second predetermined number of second inverters each having a second pull-up transistor and a second pull-down transistor, the second pull-up transistor having a large size and the second pull-down transistor having a small size wherein the first and second inverters are alternately serially connected such that an output signal from a first inverter is an input signal to a second inverter and the first inverter in a first position is responsive to the clock signal.
Similarly, the second delay and clock generating circuit comprises a second delay circuit for generating a second delay pulse, the second delay pulse making the first change in logic states the first delay time after the inverted clock signal makes a corresponding first change in logic states and making the second change in logic states the second delay time after the inverted clock signal makes a corresponding second change in logic states and a third logic gate for generating the second internal clock signal by logically manipulating the second delay pulse and the inverted clock signal. The second delay circuit includes a second plurality of serially connected inverters. The second plurality of serially connected inverters comprises a third predetermined number of third inverters each having a third pull-up transistor and a third pull-down transistor, the third pull-up transistor having a small size and the third pull-down transistor having a large size. Also included in the second plurality of serially connected inverters is a fourth predetermined number of fourth inverters each having a fourth pull-up transistor and a fourth pull-down transistor, the fourth pull-up transistor having a large size and the fourth pull-down transistor having a small size wherein the third and fourth inverters are alternately serially connected such that an output signal from a third inverter is an input signal to a fourth inverter and the third inverter in a first position is responsive to the inverted clock signal.
The first logic gate may be an OR gate, the second logic gate may be NOR gate, and the third logic gate may be a NOR gate and wherein the stop signal is the logic-OR of the first and second internal clock signals. Alternatively, the first logic gate may be a NOR gate, the second logic gate may be a NOR gate, and the third logic gate may be a NOR gate and wherein the stop signal is the logic-NOR of the first and second internal clock signals.


REFERENCES:
patent: 4717835 (1988-01-01), Takeuchi
patent: 4988901 (1991-01-01), Kamuro et al.
patent: 5146110 (1992-09-01), Kim et al.
patent: 5184032 (1993-02-01), Leach
patent: 5438550 (1995-08-01), Kim
patent: 6078193 (2000-06-01), Bazuin et al.

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