Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1998-04-21
2001-04-24
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S322000
Reexamination Certificate
active
06223297
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to clock supplying methods and information processing apparatuses, and more particularly to a clock supplying method for supplying a clock to a central processing unit (CPU) which has operation modes operating with clocks of different frequencies, and to an information processing apparatus which employs such a clock supplying method.
Recently, due to improved operation speeds of CPUs, the performance of information processing apparatuses such as personal computer using the CPU has improved considerably. However, as the operation speed of the CPU increases, the power consumption of the CPU also increases. Hence, particularly with respect to the CPU which is used in a portable information processing apparatus which uses a battery as a power source, there are two conflicting demands to be satisfied, namely, to increase the operation speed of the CPU and to reduce the power consumption of the CPU.
In the portable information processing apparatus such as a lap-top computer, the battery is used as the power source when the portable information processing apparatus is carried by the user, and it is desirable to minimize the power consumption so as to extend the serviceable life of the battery. Conventionally, in order to reduce the power consumption of the CPU, a proposed method operates the CPU at a high speed in a state where an amount of information to be processed by the CPU is large and at a low speed in a state where the amount of information to be processed by the CPU is small. More particularly, a clock supplied to the CPU is set to a high frequency when the amount of information to be processed by the CPU is large, and the clock supplied to the CPU is set to a low frequency or the supply of the clock to the CPU is stopped when the amount of information to be processed by the CPU is small.
Such a method of controlling the supply of the clock to the CPU is effective in reducing the power consumption of the information processing apparatus such as the personal computer which uses the CPU.
However, when controlling the supply of the clock to the CPU in the above described manner, the higher a maximum frequency of the clock and the higher the power consumption of the CPU, the larger a change in a current supplied to the CPU becomes when the frequency of the clock is switched from a state where the clock has a low frequency or the supply of the clock to the CPU is stopped to a state where the clock has the maximum frequency. For this reason, in order to suppress a sudden voltage drop within the CPU due to such a change in the current supplied to the CPU, a plurality of capacitors are usually provided in a power supply module of the CPU, so as to absorb the sudden voltage drop. In the case of the high-performance CPU which has recently become available, the capacitances of these capacitors are on the order of 1000 &mgr;F to 2000 &mgr;F, for example, and are extremely large.
As described above, the capacitances of the capacitors provided in the power supply module have increased due to the improved performance of the CPU. For example, in a case where a dropper type 3-terminal regulator is to supply the power supply voltage to the CPU which operates at a power supply voltage of n V, a voltage drop D described by the following formula occurs in the CPU, where C denotes a capacitance of the capacitor and R denotes a resistance in the CPU.
D=n×(1−exp(−t/RC)) V
For example, in the case of the CPU which is generally used in the personal computer, the voltage drop D must be suppressed to approximately 0.1 V to 0.2 V. Hence, in a case where the power supply voltage n is approximately 3 V, t is 1×10−5 sec by assuming that the regulator oscillates at 100 kHz, a maximum current consumption of the CPU is 6 A, and the resistance R is 0.5 &OHgr; from (3 V)/(6 A), for example, it is necessary to set the capacitance C of the capacitor to 590 &mgr;F if the voltage drop D is to be suppressed to 0.1 V, and to set the capacitance C of the capacitor to 290 &mgr;F if the voltage drop D is to be suppressed to 0.2 V.
In the calculation described above, an equivalent series resistance (ESR) of the capacitors is assumed to be zero, and thus, the actual capacitance C of the capacitor must be set to a value which is approximately 20% to 30% larger than the above described value.
Accordingly, since it is necessary to provide the capacitors having the large capacitances in order to increase the operation speed of the CPU, there were problems in that the conventional information processing apparatus becomes expensive, and in addition, it was difficult to reduce the size of the information processing apparatus because a large area is required to mount these capacitors. On the other hand, if the above described capacitors are not provided, a large voltage drop is generated when, the operation speed is switched, the operation of the CPU becomes unstable, thereby making it difficult to increase the operation speed of the CPU.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful clock supplying method and information processing apparatus, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a clock supplying method and an information processing apparatus which can satisfy two conflicting demands, namely, to increase the operation speed of the CPU and to reduce the power consumption of the CPU, by use of an inexpensive and simple structure which enables the size of the information processing apparatus to be reduced.
Still another object of the present invention is to provide a clock supplying method comprising the steps of gradually increasing a frequency of an external clock to be supplied to a central processing unit (CPU) which includes a phase locked loop (PLL) circuit from a first frequency to a second frequency within a latency time required for the PLL circuit to make a phase lock, when an operation mode of the CPU is switched from a first mode to a second mode. According to the clock supplying method of the present invention, it is possible to satisfy two conflicting demands, namely, to increase the operation speed of the CPU and to reduce the power consumption of the CPU, by use of an inexpensive and simple structure which enables the size of the information processing apparatus to be reduced.
In the clock supplying method, the first mode may be a power save mode of the CPU. In addition, an internal clock of the CPU may be stopped in the power save mode. In these cases, it is possible to effectively reduce the power consumption of the CPU.
The clock supplying method may further comprise the steps of gradually decreasing the frequency of the external clock to be supplied to the CPU from the second frequency to the first frequency, when the operation mode of the CPU is switched from the second mode to the first mode. In this case, it is possible to stabilize the operation of the CPU when the operation mode of the CPU is switched.
A further object of the present invention is to provide an information processing apparatus comprising a clock generator having a variable oscillation frequency and generating an external clock, and a central processing unit (CPU) having a phase locked loop (PLL) circuit and supplied with the external clock, where the clock generator gradually increases a frequency of the external clock from a first frequency to a second frequency within a latency time required for the PLL circuit to make a phase lock, when an operation mode of the CPU is switched from a first mode to a second mode in response to a mode instruction signal. According to the information processing apparatus of the present invention, it is possible to satisfy two conflicting demands, namely, to increase the operation speed of the CPU and to reduce the power consumption of the CPU, by use of an inexpensive and simple structure which enables the size of the information processing apparat
Fujitsu Limited
Heckler Thomas M.
Staas & Halsey , LLP
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