Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2005-08-23
2005-08-23
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S300000, C713S320000, C713S324000, C713S600000
Reexamination Certificate
active
06934870
ABSTRACT:
A clock management scheme for an 802.11 MAC on a PCI or Cardbus bus that works in conjunction with industry standardized power mechanisms. The scheme involves enabling and disabling the main clock in coordination with IEEE 802.11 protocols and is compatible with ACPI power management and configuration interface specification. When the main clock is disabled the MAC and supporting hardware can run off either a lower frequency oscillator or the bus clock. The bus clock is automatically used when it is required by accesses by the host to the card.
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Browne Lynne H.
Patel Anand B.
Tucker Ellis & West LLP
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