Clock loss detector

Details Clock loss detector Clock loss detector

1999-11-29

2000-12-19

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 95, 327 18, 327 20, H03K 1900

Patent

active

061631728

ABSTRACT:
A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when docks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.

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