Clock logic domino circuits for high-speed and energy...

Details Clock logic domino circuits for high-speed and energy... Clock logic domino circuits for high-speed and energy...

2006-10-17

2006-10-17

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000

Reexamination Certificate

active

07123056

ABSTRACT:
A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.

REFERENCES:
patent: 3857045 (1974-12-01), Low et al.
patent: 3999081 (1976-12-01), Nakajima
patent: 5426383 (1995-06-01), Kumar
patent: 6265899 (2001-07-01), Abdel-Hafeez et al.

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