Clock identification and reproduction circuit

Details Clock identification and reproduction circuit Clock identification and reproduction circuit

1999-08-25

2004-01-20

Fan, Chieh M. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S294000, C375S328000, C327S159000, C713S500000

Reexamination Certificate

active

06680992

ABSTRACT:

BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock identification and reproduction circuit and, more particularly, to a clock identification and reproduction circuit for reproducing a clock signal from a high-speed NRZ signal.
2. Description of the Related Art
Used as a signal for high-speed communication such as optical communication is an NRZ signal, in which a data signal contains no clock signal component in general. A reception IC therefore requires a clock identification and reproduction circuit which not only amplifies a data signal but also identifies a clock signal synchronizing with a data signal to reproduce a clock signal within the circuit.
FIG. 9
is a block diagram showing structure of a clock identification and reproduction circuit according to the present invention and conventional art.
With reference to
FIG. 9
, the clock identification and reproduction circuit includes a feedback loop composed of a phase comparator
20
, a filter
30
and a VCO (voltage controlled oscillator)
40
.
The phase comparator
20
compares a phase of a data signal from an input terminal
10
and that of a clock signal of the VCO
40
to generate an output voltage according to a phase difference. Then, after the filter
30
limits a bandwidth of the output voltage, the output voltage is fed back as a voltage for controlling a clock signal of the VCO
40
. By this feedback loop, a clock signal of the VCO
40
synchronizing with a data signal can be obtained.
Known as a conventional example of such a clock identification and reproduction circuit is the circuit structure invented by C. R. Hogge, Jr. (see C. R. Hogge, Jr., “A Self Correcting Clock Recovery Circuit”, Journal of Lightwave Tech., Vol. LT-3, No. 6, 1985, P1312).
FIG. 10
is a block diagram showing circuit structure of the conventional clock identification and reproduction circuit invented by C. R. Hogge, Jr.
In the following, operation of the circuit will be described.
A data signal is applied from an input terminal
10
to a first D-type flip-flop
80
a
and output from the first D-type flip-flop
80
a
with a clock signal of a VCO
40
as a latch timing clock.
The input terminal
10
and a first D-type flip-flop output terminal
75
a
are connected to a first EXOR gate
86
and an EXOR signal of the applied data signal and the output of the first D-type flip-flop
80
a
is output to a first EXOR gate output terminal
87
.
Accordingly, an output pulse width of this EXOR signal will vary according to a difference in phase between the clock signal of the VCO
40
and the data signal and be used as a comparison pulse signal.
In addition, the output of the first D-type flip-flop
80
a
is applied through the first D-type flip-flop output terminal
75
a
to a second D-type flip-flop
90
a
and output from the second D-type flip-flop
90
a
to a data output terminal
70
with an inversion of the clock signal of the VCO
40
as a latch timing clock.
The first D-type flip-flop output terminal
75
a
and the data output terminal
70
are connected to a second EXOR gate
96
and an EXOR signal of the output of the first D-type flip-flop
80
a
and the output of the second D-type flip-flop
90
a
is output to a second EXOR gate output terminal
97
.
Since this output signal constantly has a fixed pulse width regardless of a phase difference of a clock signal from that of a data signal, the output signal will be used as a reference pulse signal.
Accordingly, comparison with a comparison pulse signal results in quantitatively finding a phase difference.
FIGS. 11 and 12
are timing charts for use in explaining processing with respect to each signal of the clock identification and reproduction circuit according to conventional art.
In the processing with respect to each signal of this clock identification and reproduction circuit according to conventional art, a data signal (a) applied through the input terminal
10
is latched by a clock signal (b) to obtain a comparison pulse signal (c) from the data signal (a) and the latched output (c).
In addition, the latched output (c) is again latched (e) by an inverted clock signal (d) to obtain a reference pulse signal (g).
FIG. 11
is for use in explaining the processing executed when a phase of a clock signal leads over that of a data signal. In this case, a comparison pulse signal (f) is generated whose width is smaller than a half cycle of a clock.
On the other hand,
FIG. 12
is for use in explaining the processing executed when a phase of a clock signal lags behind that of a data signal. In this case, a comparison pulse signal (f) is generated whose width is larger than a half cycle of a clock.
Accordingly, after applying the comparison pulse signal (f) and the reference pulse signal (g) to an adder
100
a
to conduct addition (subtraction), by removing a high-frequency signal component by the filter
30
, the signal can be converted into an input voltage for controlling a clock signal of the VCO
40
. Thus structured feedback loop enables reproduction of a clock signal synchronizing with a data signal.
Since in the conventional clock identification and reproduction circuit shown in
FIG. 10
, the more the phase of a clock signal of the VCO
40
leads over that of an input data signal, the smaller a width of a comparison pulse signal generated at the first EXOR gate output terminal
87
becomes as illustrated in
FIG. 11
(f), the first EXOR gate
86
requires to have a fast enough response.
In addition, as the clock signal has its phase more lagging behind that of the data signal as illustrated in
FIG. 12
, the interval of the comparison pulse signal (f) becomes shorter and shorter. Also in this case, if a response speed of the EXOR circuit is not high enough, waveforms might interfere with each other due to a drop of waveforms, making quantitative discrimination of a phase difference impossible.
Therefore, when a response speed of the EXOR circuit is not sufficient, a margin of a latch timing of a high-speed data signal will become narrow to make clock identification and reproduction difficult and degrade reliability of circuit operation. Another problem is the reduction in the flexibility of circuit design.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a clock identification and reproduction circuit including a phase comparison circuit capable of quantitatively obtaining a phase difference between a data signal and a clock signal without requiring high-speediness of the circuit.
A second object of the present invention is to provide a clock identification and reproduction circuit which is capable of conducting highly reliable clock identification without a possibility of interference of a waveform due to a latch timing and whose flexibility of circuit design is high.
According to the first aspect of the invention, a clock identification and reproduction circuit which synchronizes a clock signal with an input signal, comprises
a voltage controlled generator for generating the clock signal,
a phase comparator for detecting a phase difference between the input signal and the clock signal to generate a phase difference signal according to the phase difference, and
a filter for synchronizing a phase of the clock signal of the voltage controlled generator in response to the phase difference signal, wherein
the phase comparator generates the phase difference signal when a specific pulse waveform of a pulse of the input signal changes.
In the preferred construction, the phase comparator generates the phase difference signal when
the pulse waveform of the input signal changes from “0” to “1”.
In another preferred construction, the phase comparator comprises
a first D-type flip-flop circuit for latching and outputting the input signal with the clock signal as a latch timing,
a second D-type flip-flop circuit for latching and outputting the output from the first D-type flip-flop circuit with an inversion of the clock signal as a latch timing,
a first logical product gate for outputting a logical product of the input

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