Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2007-05-08
2007-05-08
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S500000, C713S502000, C713S503000, C713S600000, C327S141000, C327S144000, C327S147000, C327S156000, C331S002000, C331S046000, C331S051000
Reexamination Certificate
active
10457149
ABSTRACT:
A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.
REFERENCES:
patent: 6111712 (2000-08-01), Vishakhadatta et al.
patent: 6118316 (2000-09-01), Tamamura et al.
patent: 6566921 (2003-05-01), Boerstler et al.
patent: 6703876 (2004-03-01), Fujiwara et al.
Fujiwara Masayu
Onishi Masaki
Hogan & Hartson LLP
Rohm & Co., Ltd.
Trujillo James K.
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