Clock generation in a multi-chip computer system

Details Clock generation in a multi-chip computer system Clock generation in a multi-chip computer system

1991-06-14

1994-04-12

Shaw, Dale M.

Boots, shoes, and leggings

3649458, G06F 104

Patent

active

053033655

ABSTRACT:
The invention relates to a multi-chip computersystem with master-slave latches. It is known to provide all latches on all chips with two clock pulses, respectively. With the help of the latches the digital signals are pipelined through the logic gates on the chip. Due to tolerances, the edges which control the masters and the slaves have a skew. According to the invention, one of the two clock pulses is generated on the chip itself, respectively, by ANDing an auxiliary clock pulse with the other of the two clock pulses. This has the result, that the above mentioned edges of the two clock pulses occur almost at the same time with the consequence that the frequency of the clock pulses can be increased.

REFERENCES:
patent: 4409671 (1983-10-01), Daniels et al.
patent: 4419739 (1983-12-01), Blum
patent: 4745302 (1988-05-01), Hanawa et al.
patent: 4799040 (1989-01-01), Yanagi
IBM TDB, vol. 31, No. 12, May 1989 On-Chip LSSD Clock Generator with Zero Gap Between Master to Slave Clocks.
IBM TDB, vol. 27, No. 8, Jan. 1985 Synchronization of LSSD System Clocks to Asynchronous Signals.

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