Clock generation for testing of integrated circuits

Details Clock generation for testing of integrated circuits Clock generation for testing of integrated circuits

1996-10-18

1998-09-08

Beausoliel, Jr., Robert W.

Excavating

G01R 3128

Patent

active

058056084

ABSTRACT:
In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.

REFERENCES:
patent: 4860290 (1989-08-01), Daniels et al.
patent: 5313470 (1994-05-01), Simpson
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5497378 (1996-03-01), Amini et al.
patent: 5510704 (1996-04-01), Parker et al.
patent: 5519715 (1996-05-01), Hao et al.
patent: 5524114 (1996-06-01), Peng
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5608736 (1997-03-01), Bradford et al.
patent: 5614838 (1997-03-01), Jaber et al.
patent: 5623503 (1997-04-01), Rutkowski
Texas Instruments, Boundary-Scan Architecture and IEEE Std 1149.1 (from Chapter 3 of TI's IEEE 1149.1 Testability Primer, SSYA002B) (Nov. 1996).
IEEE Computer Society, "IEEE Standard Test Access Port and Boundary-Scan Architecture", Published by the Institute of Electrical and Electronics Engineers, Inc. (1990), including 1149.1a (Oct. 21, 1993) and 1149.1b (Mar. 1, 1995).
Maunder and Tulloss, "The Test Access Port and Boundary-Scan Architecture", Published by the IEEE Computer Society Press, Los Alamitos, California (1990).

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