Clock generation for multiple clock domains

Details Clock generation for multiple clock domains Clock generation for multiple clock domains

2011-05-17

2011-05-17

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S500000, C713S502000

Reexamination Certificate

active

07945803

ABSTRACT:
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.

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patent: 2005/0229066 (2005-10-01), Wolff et al.
patent: 2005/0262374 (2005-11-01), Shinkawa
patent: 2006/0064616 (2006-03-01), Rajski et al.
patent: 0 547 768 (1993-06-01), None

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