Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2006-01-24
2006-01-24
Elamin, A. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C375S257000, C375S372000, C362S060000, C362S060000, C327S003000, C327S010000
Reexamination Certificate
active
06990597
ABSTRACT:
A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the same. The clock generation circuit has: serially-connected inversion circuits IV0to IV4in which an output of IV4is connected to an input of IV0by a feedback line FL; and buffer circuits BF0to BF4which receives outputs from IV0to IV4. The inversion circuits IV0to IV4are disposed along a line LN1and the buffer circuits BF0to BF4are disposed along a line LN2that is parallel to the feedback line FL but different from LN1. Dummy lines DL0to DL3each of which having parasitic capacitance that is equal to that of the feedback line FL are connected to the inversion circuits IV0to IV3, to equalize the phase differences between clocks CK0to CK4. The feedback line FL and the dummy lines DL0to DL3are disposed in a region between the inversion circuits IV0to IV4and the buffer circuits BF0to BF4. Between which edges of multi-phase clocks an edge of data (data transferred in USB 2.0 HS mode) is located is detected, and a clock selected on the basis of edge detection information is set as a sampling clock.
REFERENCES:
patent: 5341031 (1994-08-01), Kinoshita et al.
patent: 5553104 (1996-09-01), Takashi et al.
patent: 5793246 (1998-08-01), Vest et al.
patent: 5872741 (1999-02-01), Abo
patent: 5963501 (1999-10-01), Lee et al.
patent: 6084805 (2000-07-01), Pawlowski
patent: 6138246 (2000-10-01), Petty
patent: 6147532 (2000-11-01), Ueda
patent: 6169704 (2001-01-01), Sher
patent: 6236260 (2001-05-01), Vest et al.
patent: 6256260 (2001-07-01), Shim et al.
patent: 6346828 (2002-02-01), Rosen et al.
patent: 6429713 (2002-08-01), Nakaizumi
patent: 6445644 (2002-09-01), Sher
patent: 6518808 (2003-02-01), Shimoda
patent: 6577554 (2003-06-01), Song et al.
patent: 6603817 (2003-08-01), Hamamoto et al.
patent: A 63-076640 (1988-04-01), None
patent: A 01-296734 (1989-11-01), None
patent: A 02-107036 (1990-04-01), None
patent: 8-274592 (1996-10-01), None
patent: A 09-036849 (1997-02-01), None
patent: A 10-070441 (1998-03-01), None
patent: A 11-308204 (1999-05-01), None
Lueker, Jon et al., USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Verson 1.0rc, Apr. 25, 2000.
U.S. Appl. No. 09/977,338, filed Oct. 2001, Kamihara.
Abe Akira
Kamihara Yoshiyuki
Kasahara Shoichiro
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