Clock generation circuit

Details Clock generation circuit Clock generation circuit

2006-03-06

2008-09-02

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S600000

Reexamination Certificate

active

07421610

ABSTRACT:
A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.

REFERENCES:
patent: 6518788 (2003-02-01), Kasahara
patent: 6539509 (2003-03-01), Teene
patent: 6895523 (2005-05-01), Otsuka
patent: 7082546 (2006-07-01), Schoch
patent: 2005/0289379 (2005-12-01), Teutsch et al.
patent: 10-177060 (1998-06-01), None
patent: 2003-216671 (2003-07-01), None

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