Clock generation

Details Clock generation Clock generation

1997-12-29

2001-02-06

Butler, Dennis M. (Department: 2787)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000, C713S502000

Reexamination Certificate

active

06185691

ABSTRACT:

BACKGROUND
The invention relates to generating clocks for use in electronic systems.
Clocks are used throughout an electronic system, such as a computer system, to synchronize events communicated among chips in a system as well as among devices inside a chip. At the system level, a master clock generator provides a master clock which is typically of a very high frequency. This master clock is divided down and provided to components throughout the system. At the chip level, a phase locked loop (PLL) circuit generates internal clocks for use by circuitry in the chip. The clocks generated by the PLL circuit are synchronized to an external clock.
Both at the system level and at the chip level, different frequency clocks are typically required for different parts of the system or chip. Clock dividers are used to divide a clock to a desired lower frequency clock. Thus, for example, a main clock can be divided by 2, 3, 5, 6, and so forth. If the main clock has generally a 50% or half duty cycle (i.e., the clock pulse high width is the same as the clock pulse low width), division by an even number (e.g., 2, 4) will result in a divided clock also having generally a 50% duty cycle. However, using typical clock dividers, division by an odd number may result in clocks having duty cycle that is not at 50%. For example, a divide by three clock may have a high pulse width to low pulse width ratio of 1:2, that is, the clock's high pulse width is half its low pulse width.
SUMMARY
The invention is directed to generating a divided clock from a main clock, with the divided clock generally having a half duty cycle.
In general, in one aspect, the invention features a clocking circuit for generating an output clock. The clocking circuit includes a master counting device coupled to receive a first clock and a slave counting device coupled to receive a second clock. The second clock is an inverted version of the first clock. A decoder receives outputs of the master and slave counting devices to generate an output clock that is a divided version of the first clock.
In general, in another aspect, the invention features a method of generating a divided clock from a main clock. A master counter is advanced in response to the main clock, and a slave counter is advanced in response to an inverted version of the main clock. Output bits from the master and slave counters are decoded to generate the divided clock.
Other features and advantages will become apparent from the following description and from the claims.


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patent: 5914996 (1999-06-01), Huang

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