Clock generating system generating clock based on value...

Details Clock generating system generating clock based on value... Clock generating system generating clock based on value...

1999-04-21

2002-04-30

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output process timing

C713S500000, C713S501000, C713S502000, C713S503000, C386S349000, C369S047360

Reexamination Certificate

active

06381660

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock generating apparatus that receives time information and generates a clock signal in accordance with the time information, and also relates to a method of generating a clock signal.
2. Prior Art
Digital serial communication according to IEEE-1394 has been widely applied in recent years. This type of communication permits packet communication, i.e., transmission of packets in which system time (time information) is added to audio data. Each of the packets includes system time and audio data.
FIG. 1
is a time chart showing a conventional packet communication method. In the example shown in
FIG. 1
, packet P
1
, packet P
2
, packet P
3
and packet P
4
are transmitted in the mentioned order. The packet P
1
includes system time T1 and audio data D
1
, and the packet P
2
includes system time T2 and audio data D
2
. Similarly, the packet P
3
includes system time T3 and audio data D
3
, and the packet P
4
includes system time T4 and audio data D
4
. In the following description, the packets P
1
-P
4
, system times T1-T4, and the audio data D
1
-D
4
will be generally called “packet P”, “system time T”, and “audio data” D, respectively.
FIG. 2
shows the construction of a conventional receiver system according to IEEE-1394. The system of
FIG. 2
includes a FIFO (SYTR×FIFO)
11
for receiving the system time, which serves as a buffer that stores and outputs the system time T in the packet P in a first-in first-out manner. The audio data D in the packet P is stored in another FIFO (not illustrated).
A time stamp register
16
serves to store each system time T received from the FIFO
11
, as a time stamp TT. Initially, the system time T1 of the first packet P
1
is stored in the time stamp register
16
.
A comparator
17
is adapted to compare the time stamp TT stored in the time stamp register
16
, with a system clock signal CK generated by a system cycle timer
18
, and generates a clock signal Ft, or one of pulses Ft
1
-Ft
4
(FIG.
1
), when the time stamp TT coincides with the system clock signal CK. Namely, the clock signal Ft contains individual pulses that represent the timing in which the time stamps TT are synchronized with the system clock signal CK.
The clock signal Ft has a frequency of, for example, 6 kHz. The system clock signal CK has a frequency of, for example, 24.576 MHz.
A phase lock loop (PLL) circuit
19
has a voltage-controlled oscillator (VCO), and serves to generate a word clock signal Fs (
FIG. 1
) comprising clock pulses that are in synchronism with the clock signal Ft. The word clock signal Fs has a frequency of, for example, 48 kHz. The audio data D contained in the packet P is reproduced in synchronism with the word clock signal Fs. Namely, the sampling frequency of the audio data D is, for example, 48 kHz.
The packet P includes system time T and audio data D. The audio data D contains eight samples (or eight blocks) of data, and its sampling frequency is, for example, 48 kHz. The system time T corresponds to the reproduction time of the first sample data. Accordingly, the frequency of the clock signal Ft generated by the comparator
17
is 6 kHz, which is obtained by dividing the sampling frequency, 48 kHz, by eight.
The PLL
19
generates the word clock signal Fs based on the clock signal Ft. The frequency of the word clock signal Fs is eight times as high as that of the clock signal Ft, and is equal to the sampling frequency, i.e., 48 kHz.
Where the sampling frequency is 48 kHz, a difference in the value of the system time T between two successive packets P is 1400 in hexadecimal. In the following description, the hexadecimal value or number is followed by “h”.
As shown in
FIG. 1
, the system time T1 has a value of 0, the system time T2 has a value of 1400 h, the system time T3 has a value of 2800 h, and the system time T4 has a value of 3C00h.
As described above, the packets P are transmitted at the frequency of ⅙ kHz, and therefore the pulses Ft
1
-Ft
4
of the clock signal Ft are also generated at the frequency of ⅙ kHz. The word clock signal Fs having the frequency of 48 kHz is generated based on the clock signal Ft of 6 kHz. The audio data D is reproduced in synchronism with the word clock signal Fs.
FIG. 3
is a time chart showing known packet communication when a series of packets is interrupted during the communication.
Suppose no packet, such as packet P
3
and packet P
4
as shown in
FIG. 1
, follows after packet P
1
and packet P
2
are transmitted, and packet communication is resumed after a while. This situation may happen when the audio data D is temporarily finished, or sound corresponding to the audio data is silent.
A pulse Ft
1
is generated in response to the system time T1 in the packet P
1
, and a pulse Ft
2
is generated in response to the system time T2 in the packet P
2
. Since no further packet follows the packet P
2
, subsequent pulses (e.g., pulse Ft
3
and pulse Ft
4
as indicated by dotted lines in
FIG. 3
) are not generated.
The word clock signal Fs has a stable clock region Fs
1
and an unstable clock region Fs
2
. The clock region Fs
1
is stable since clock pulses in this region are generated in synchronism with the pulses Ft
1
and Ft
2
. The clock region Fs
2
, on the other hand, is unstable since no clock pulses, such as Ft
3
and Ft
4
in
FIG. 1
, are present for synchronization with the pulses in this region Fs
2
. Thus, the pulses in the clock region Fs
2
are shifted in phase with time, and the frequency of the work clock signal Fs changes with time.
The audio data D are processed in synchronism with the word clock signal Fs, and a processor that performs equalization, sound-field processing, and the like, produces parameters that depend upon the word clock signal Fs. If the word clock signal Fs is disturbed or comes out of phase, or the frequency of the word clock signal Fs changes, therefore, the parameters need to be re-set. In the meantime, the processor mutes audio output, or stops generating sound.
The muted state as described above occurs each time the packet communication is temporarily interrupted, or a packet receiving channel is switched from one to another, or a communication cable is plugged out or disconnected. In the case where a software of a computer is used for performing operations of transmission of packets, packet transmission may be stopped when no data to be transmitted is present. During this time, a receiver system is set to mute audio output or sound.
If muting takes place while audio data is being reproduced, sound corresponding to the audio data breaks off in the middle of reproduction, and thus the audio data cannot be reproduced as it is. Also, a listener may find reproduced sound uncomfortable upon occurrence of muting.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide a clock generating apparatus that is able to generate a stable clock signal, and a method of generating such a clock signal.
To attain the above object, the present invention provides a clock generating apparatus comprising an input device that sequentially receives first time information, and second time information that is of the same type of the first time information and immediately follows the first time information, a difference determining device that determines a difference between the first time information and the second time information, and a clock generating device that generates a clock signal based on the first time information when the input device receives the first time information, generates a clock signal based on the second time information when the input device receives the second time information, and thereafter generates a clock signal based on a value obtained by adding the second time information and the difference between the first time information and the second time information.
Preferably, the clock generating device generates the clock signal based on the value obtained by adding the second time information and the difference between th

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