Clock generating circuits that utilize analog pump signals to pr

Details Clock generating circuits that utilize analog pump signals to pr Clock generating circuits that utilize analog pump signals to pr

1999-08-26

2000-10-31

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523008, G11C 1300

Patent

active

061412929

ABSTRACT:
Clock generating circuits include a clock buffer, a delay mirror circuit (DMC), a clock frequency divider circuit and a clock generator circuit. The clock buffer is responsive to an external clock signal EXTCLK and generates a buffered clock signal ICLK in response to the external clock signal EXTCLK. The buffered clock signal ICLK is delayed relative to the external clock signal EXTCLK by a fixed buffer delay time "dtb". The delay mirror circuit (DMC) is responsive to the buffered clock signal ICLK and generates a delayed clock signal IDCLK. The delayed clock signal IDCLK is delayed relative to the buffered clock signal ICLK by a fixed delay-mirror time "dtot". The clock frequency divider circuit is responsive to the buffered clock signal ICLK and the delayed clock signal IDCLK. The clock frequency divider circuit includes first and second divider devices that generate first and second divided clock signals VDIV1 and VDIV2, respectively. The clock generator circuit is responsive to VDIV1 and VDIV2 and includes a control signal generator, an analog pump signal generator and a driver circuit. Based on this configuration of the above-described circuits, only 2 clock periods are required before the rising edge of the internal clock signal INTCLK is in-sync and in-phase with the external clock signal EXTCLK.

REFERENCES:
patent: 5666323 (1997-09-01), Zagar
patent: 5742194 (1998-04-01), Saeki
patent: 5748554 (1998-05-01), Barth et al.
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5818788 (1998-10-01), Kimura et al.
patent: 5822268 (1998-10-01), Kirihata
patent: 5892730 (1999-04-01), Sato et al.
Saeki et al., A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM With Synchronous Mirror Delay, IEEE Journal of Solid State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1656-1665.
Han et al., Skew Minimizing Techniques for the Synchronous DRAMs Beyond 256 M-bit, Symp. VLSI Circuits, Jun. 1996, pp. 192-193.

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