Clock generating circuits controlling activation of a delay...

Details Clock generating circuits controlling activation of a delay... Clock generating circuits controlling activation of a delay...

2001-06-19

2003-02-25

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S227000, C365S229000, C365S236000

Reexamination Certificate

active

06525988

ABSTRACT:

RELATED APPLICATION
This application claims priority from Korean Application No. 00-70489, filed Nov. 24, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to semiconductor memory devices containing delay locked loop circuits and methods of operating same.
BACKGROUND OF THE INVENTION
Many integrated circuit devices (e.g., memory devices) operate in-sync with externally supplied clock signals by generating one or more internal clock signals that are preferably phase locked with the external clock signal and with each other. As will be understood by those skilled in the art, accurate phase locking of clock signals can be especially important for integrated circuit devices, such as semiconductor memory devices, that operate at high frequencies. Such integrated circuit devices may include merged memory with logic (MML) devices, Rambus DRAM devices and double data rate synchronous DRAM devices (DDR-SDRAM). Semiconductor memory devices such as a selected circuit DRAM generally provide a power down mode for deactivating selected circuit blocks inside the DRAM. In other words, some, but not all, of the circuit blocks inside the DRAM may be deactivated in order to reduce power consumption by the DRAM.
The power down modes of a DRAM may include an active power down mode, a precharge power down mode, and a self-refresh mode. When the DRAM is in the active power down mode or the precharge power down mode, all input buffers excluding an input buffer connected to a system clock (CLK) pin and an input buffer connected to a clock enable (CKE) pin are typically deactivated. Therefore, power consumption may be reduced in the active power down mode and the precharge power down mode. When the active power down mode or the precharge power down mode proceed for more than a predetermined time, all the data stored in the DRAM is generally lost.
In the self refresh mode, the data stored in the DRAM is refreshed and maintained, typically by a signal automatically generated inside the DRAM. This distinguishes the self refresh mode from the active power down mode and the precharge power down mode. In the self refresh mode, a delay locked loop circuit of the DRAM is also typically deactivated.
The DRAM generally also has a standby mode (or an idle mode), which is a preparatory state, in which an active command or a mode register set (MRS) command can typically be performed. When the mode of the DRAM transitions from the self refresh mode to the standby mode, the DRAM generally immediately starts operating the delay locked loop circuit and synchronizing a system clock and an internal clock for several hundred cycles. The delay locked loop continues to operate during the standby mode.
Thus, in a conventional DRAM, because the delay locked loop circuit generally continuously operates in the standby mode, power consumption by the DRAM may be increased.
SUMMARY OF THE INVENTION
In accordance with various embodiments of the present invention, clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the delay locked loop circuit for a predetermined time when the semiconductor memory device transitions from a self refresh mode, in which the DLL circuit is deactivated, to a standby mode. The control circuit may also be configured to deactivate the DLL circuit when the semiconductor memory device transitions from a power down mode, in which the DLL circuit is activated, to the standby mode. The semiconductor memory device may be a dynamic random access memory device and the predetermined time may be a number of clock cycles of the internal clock signal.
In further embodiments of the present invention, the control circuit includes a first control circuit that generates a control signal that is enabled for the predetermined time responsive to a first signal that indicates the semiconductor memory device has transitioned from the self refresh mode to the standby mode. A second control circuit activates the DLL circuit responsive to the first signal and deactivates the DLL circuit responsive to the control signal and responsive to a second signal that indicates the semiconductor memory device has transitioned from the power down mode to the standby mode.
In other embodiments of the present invention, the first control circuit includes a control signal generating circuit that outputs the control signal responsive to the first signal and a time out signal. The first control circuit further includes a counter circuit that generates the time out signal responsive to the control signal. The second control circuit may include a set pulse generating circuit that generates a set pulse signal responsive to the first signal and a reset pulse generating circuit that generates a reset pulse signal responsive to the control signal. A standby signal generating circuit activates the DLL circuit responsive to the set pulse and deactivates the DLL circuit responsive to the reset pulse signal and responsive to the second signal.
The set pulse generating circuit may include a delay circuit that determines a pulse width of the set pulse signal. The reset pulse generating circuit may include a delay circuit that determines a pulse width of the reset pulse signal. The predetermined time during which the DLL is activated after the standby mode is entered from the self refresh mode may be no less than an expected lock time for the DLL circuit. The predetermined time may be specified as a number of clock cycles of the internal clock signal. The power down mode may be a precharge power down mode.
In further aspects of the present invention, methods are provided for controlling a clock generating circuit of a semiconductor memory device. A delay locked loop (DLL) circuit of the clock generating circuit is activated when the semiconductor memory device transitions to a standby mode from a self refresh mode in which the DLL circuit is deactivated. The DLL circuit is then deactivated a predetermined time after the semiconductor memory device transitions to the standby mode from the self refresh mode. In further embodiments, the DLL circuit is also deactivated when the semiconductor memory device transitions to the standby mode from a power down mode in which the DLL circuit is activated.
In yet other embodiments of the present invention, semiconductor memory devices are provided which have a self refresh mode, a precharge power down mode, and a standby mode and which operate in synchronization with a system clock signal. The semiconductor memory device includes a delay locked loop circuit for generating an internal clock signal in synchronization with the system clock signal. The device further includes a control circuit for activating the delay locked loop circuit during a predetermined clock cycle of the internal clock signal when the mode of the semiconductor memory device is converted from the self refresh mode into the standby mode and then, deactivating the delay locked loop circuit and deactivating the delay locked loop circuit when the mode of the semiconductor memory device is converted from the precharge power down mode into the standby mode.


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