Clock gating system and method

Details Clock gating system and method Clock gating system and method

2011-03-08

2011-03-08

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

07902878

ABSTRACT:
A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

REFERENCES:
patent: 5598112 (1997-01-01), Phillips
patent: 5822700 (1998-10-01), Hult et al.
patent: 5883529 (1999-03-01), Kumata et al.
patent: 5920547 (1999-07-01), Werth
patent: 5936449 (1999-08-01), Huang
patent: 6133762 (2000-10-01), Hill
patent: 6157839 (2000-12-01), Cerwall et al.
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6456115 (2002-09-01), Li et al.
patent: 6552272 (2003-04-01), Sheng et al.
patent: 6552572 (2003-04-01), Cheung
patent: 7068080 (2006-06-01), Sanders
patent: 7109776 (2006-09-01), Tschanz et al.
patent: 7365575 (2008-04-01), Kim
patent: 7450587 (2008-11-01), Gruhn et al.
patent: 7519016 (2009-04-01), Lee et al.
patent: 7587686 (2009-09-01), Schleicher, II
patent: 7612597 (2009-11-01), Matsumoto
patent: 7639057 (2009-12-01), Su
patent: 2003/0228865 (2003-12-01), Terry
patent: 2004/0237054 (2004-11-01), Tsai
patent: 2006/0097754 (2006-05-01), Kim
patent: 2007/0024318 (2007-02-01), Mamidipaka
patent: 2420034 (2006-05-01), None
patent: 2005036422 (2005-04-01), None
Harris, David. “Skew-Tolerant Circuit Design,” 2001, pp. 52-55, Academic Press.
Mohd, B. et al. “Reducing Flip-Flop Power for DSP Design,” Third Annual Austin Conference on Integrated Systems and Circuits, Austin, TX, May 2008, pp. 34-39.
International Search Report—PCT/US2009/043913, International Search Authority—European Patent Office Jul. 27, 2010.
Written Opinion—PCT/US2009/043913, International Search Authority—European Patent Office Jul. 27, 2010.

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