Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2006-08-22
2006-08-22
Le, Don P. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S046000
Reexamination Certificate
active
07095251
ABSTRACT:
There is disclosed a clock gating structure for a synchronous circuit comprising a plurality of clocked state holding elements, the clocked gating structure including at least one full-cycle clock gating cell and at least one half-cycle clock gating cell, and a method for designing and controlling such.
REFERENCES:
patent: 5923188 (1999-07-01), Kametani et al.
patent: 6204695 (2001-03-01), Alfke et al.
patent: 6552572 (2003-04-01), Cheung et al.
patent: 6608501 (2003-08-01), Rosen
patent: 6822478 (2004-11-01), Elappuparackal
patent: 6831482 (2004-12-01), Cunningham et al.
patent: 6927604 (2005-08-01), Boerstler et al.
Cunningham Paul Alexander
Wilcox Stephen Paul
Azuro (UK) Limited
Gibbons Del Deo Dolan Griffinger & Vecchione
Le Don P.
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