Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-06-18
2001-03-20
Nelms, David (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C327S141000
Reexamination Certificate
active
06204695
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a user-defined logic device. More specifically, the present invention relates to a circuit for reducing power consumption within a user-defined logic device.
BACKGROUND OF THE INVENTION
The timing of events is key to proper processing within user-defined logic devices. Accordingly, a single clock is used as a reference to determine the timing of events. Each process may be clocked from a single distributed clock signal, providing highly synchronized processing.
However, not all processes are active at all times. Therefore, some processes do not require a continuous clock signal. Continuously providing the primary clock signal to a process that does not require such adds unnecessarily to the power consumption of the chip. A significant cause of power consumption within a user-defined logic device is the power required to distribute the primary clock signal throughout the chip.
To lessen this power consumption, some users of user-defined logic devices utilize a portion of the resources of the logic device to “gate” the primary clock. A clock is gated when the regular clock pulse waveform is translated to a constant value output. For example, when a primary clock signal has a traditional square waveform, the gated clock signal has a constant logic value (e.g., a constant logic low value). Because the power required to provide a constant logic value to a process is less than the power required to provide a square waveform, the power consumption of the chip is reduced.
User-defined logic device resources typically use individual clock enable (CE) controls to control flip-flops and registers. These individual clock enable controls can be used to implement clock gating circuitry within the logic of the user-defined logic device. However, this method of gating the clock signal undesirably requires utilization of core logic resources of the user-defined logic device to form these clock enable controls.
Because flip-flops and registers respond to either the rising or falling edge of a clock signal, it would be desirable to have control over the state of the gated clock signal. Control over the state of the gated clock signal provides a user with control of the state of the flip-flops and registers receiving the gated clock signal. Thus, it would be desirable to control the logic value of the gated clock signal.
The high power consumption of a continuously running clock forces many users to create their own circuits to gate the global clock. This means that many users create their own methods of suspending the clock signal to a process to prevent the power consumption caused by the unnecessary provision of the primary clock to that process. These user-created methods can yield undesirable effects including glitches and runt pulses in the gated clock signal.
It would therefore be desirable to have a clock gating circuit for a user-defined logic device that does not consume large amounts of device resources, provides user control over the logic value of the gated clock, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses.
SUMMARY
In one embodiment of the present invention, a programmable logic device includes an array of programmable logic resources, such as configurable logic blocks, and a dedicated clock gating circuit. The dedicated clock gating circuit is preferably located outside of the array of configurable logic blocks. For example, the dedicated clock gating circuit can be located at the periphery of the programmable logic device. In one embodiment, the clock gating circuit includes a storage latch that is configured to receive an input clock signal and a clock enable signal. The storage latch is configured to generate a control signal in response to the input clock signal and the clock enable signal. This control signal is used to control the gating of the input clock signal, such that a glitch-free and runt-free output clock signal is generated.
In accordance with a method of the present invention, the storage latch operates as follows to generate the control signal.
When the input clock signal is in a first logic state, the storage latch provides a control signal representative of the clock enable signal. If the state of the clock enable signal changes while the input clock signal is in the first logic state, then the control signal changes to reflect this change in the clock enable signal. In one example, if the input clock signal is in a logic low state, then the control signal has the same logic state as the clock enable signal. A logic high clock enable signal therefore results in a logic high control signal. If the clock enable signal goes low, then the control signal also goes low.
When the input clock signal transitions from the first logic state to a second logic state, the value of the clock enable signal is latched into the storage latch. This value of the clock enable signal remains latched in the storage latch as long as the input clock signal remains in the second logic state. During this time, the control signal provided by the storage latch is representative of the clock enable signal latched in the storage latch. Thus, even if the clock enable signal changes while the input clock signal is in the second logic state, the control signal does not change during this time. For example, if the clock enable signal has a logic low value when the input clock signal transitions from a logic low state to a logic high state, the logic low clock enable signal is latched in the storage latch. This logic low signal is provided as the control signal. As long as the input clock signal remains in the logic high state, the control signal maintains the logic low value, regardless of any changes in the clock enable signal.
The control signal is used to control the gating of the input clock signal. For example, the control signal can be logically ANDed with the input clock signal to create an output clock signal. The output clock signal is then routed throughout the programmable logic device.
The manner in which the control signal is generated advantageously ensures that the output clock signal does not exhibit glitches or runt pulses.
REFERENCES:
patent: 5537062 (1996-07-01), Mote, Jr.
Alfke Peter H.
Ching Alvin Y.
Frake Scott O.
Wong Jennifer
Young Steven P.
Cartier Lois D.
Nelms David
Stephenson Julie
Tran M.
Xilinx , Inc.
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