Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-31
2006-10-31
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07131092
ABSTRACT:
Clock gating circuits are disclosed in the present disclosure. Also disclosed herein are methods for designing clock gating circuits in the early stages of manufacturing. In one embodiment of a method for designing a clock gating circuit, the method comprises providing a schematic layout of a D-type flip-flop, wherein the flip-flop has a reset terminal and two latches. The method further comprises modifying the layout of the flip-flop to create a clock gating circuit.
REFERENCES:
patent: 4825097 (1989-04-01), Bazil et al.
patent: 5546035 (1996-08-01), Okamoto
patent: 5784384 (1998-07-01), Maeno
patent: 5835045 (1998-11-01), Ogawa et al.
patent: 6252448 (2001-06-01), Schober
patent: 6323709 (2001-11-01), Kulkarni et al.
patent: 6333656 (2001-12-01), Schober
patent: 6374393 (2002-04-01), Hirairi
patent: 6496050 (2002-12-01), Lloyd
patent: 6753714 (2004-06-01), Gupta
patent: 2005/0007152 (2005-01-01), Dhong et al.
patent: 2006/0109040 (2006-05-01), Clerc
patent: 2006/0170479 (2006-08-01), Hirata et al.
Dinh Paul
Parihar Suchin
VIA Technologies Inc.
LandOfFree
Clock gating circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock gating circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock gating circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3697565