Clock gated bus keeper

Details Clock gated bus keeper Clock gated bus keeper

1999-12-29

2002-11-19

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C710S100000

Reexamination Certificate

active

06484267

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to bus keepers. The invention pertains more particularly to bus keepers for buses of system-on-a-chip integrated circuits.
BACKGROUND OF THE INVENTION
The use of busses (e.g., address busses and data busses) to provide a single, data path that is shared by a plurality of data processing devices, such as memories, micro controllers, microprocessors, digital signal processors (DSPs), and peripheral devices is, of course, well known. Busses are most commonly formed on printed circuit boards and interconnect a plurality of devices mounted on the printed circuit board. The busses may also run out to connectors (for instance in a personal computer) in order to allow external devices to be coupled to the bus.
Recently, integrated circuit manufacturers have begun producing single chips containing multiple device cores of the type, e.g., memories, micro controllers, DSPs, and microprocessors, that traditionally were embodied on different chips mounted on a PCB and interconnected by one or more busses that ran on the PCB. Such a chip is commonly termed a system-on-a-chip or SoC.
SoCs also incorporate busses to provide data paths to interconnect the multiple core devices on the chip. The busses on SoCs, however, comprise conductor traces on the chip and thus tend to be much shorter in length and less sensitive to noise than printed circuit board busses. A typical SoC that would include one or more busses might be a SoC including a processor or multiprocessor that connects to several peripheral devices and/or several memory blocks (SRAM, DRAM, PROM and ROM).
Floating nodes occur when no drivers are actively connected to a node, which is a condition that is commonly associated with a node, such as a bus node, that can alternately be driven by a plurality of different devices. When a node is not actively driven, it is connected to power and ground only through the high impedance of non-conducting n and p transistors of the drivers that can drive the bus and the gate inputs of the receiving devices coupled to the bus. The voltage on the receiver input gates can drift to a critical level, V
crit
, that will cause the n and p transistors of the receivers to conduct simultaneously. This establishes a low impedance path between power and ground through the receiving device which can be a source of wasted power and possibly even destruction of the device.
In CMOS technology, the floating node problem exists usually because of one or more of three reasons, namely, (1) design oversight, (2) decoding simplification, and (3) bus turn around time (e.g., null cycles). Design oversight can occur when driver select signals are not decoded to select a default driver for one or more combinations of signal values. Such oversights can be simply a mistake or may occur when a to pre-existing design is modified for a new application and a bus driver that is no longer needed in the new design is removed from the circuit.
Floating node conditions also can be caused when the signals that select a bus driver are intentionally not decoded. This can occur when there is a large number of signals that select the bus driver and the decode logic is simplified by way of not decoding one or more default selections.
Another cause of a floating node condition is bus turnaround time specifications which often are incorporated into designs in order to prevent bus contention. Specifically, when multiple drivers can drive a single node (e.g., a bus bit line), care must be taken in the bus access protocol to prevent two devices from driving the bus simultaneously. One driver must be completely turned off before the next driver is turned on. If one driver is trying to drive the bus to a logic low level while another driver is trying to drive it to a logic high level, a very low impedance path between power and ground can be established which will destroy the device. Bus contention can occur at the point where one bus driver is turning off and another is turning on simultaneously. Specifically, it requires some finite period of time to turn a driver off or on. Differences in the delays of different drivers turning on and off and differences in the skew of the control signals selecting the drivers makes it extremely difficult to ensure that bus contention will not occur if one driver is switched off on the same clock phase that the next driver is switched on. Thus, turning drivers on and off in the same phase of a clock can cause transient bus contention.
Bus turn around time, or null cycle, is a scheme by which driver-to-driver bus contention is prevented. It refers to an allotted period of time in the bus access protocol when all drivers are turned off, i.e., the time between one driver switching off and the next driver switching on. Accordingly, bus protocols commonly include null cycles between switching of drivers on a bus. Null cycles (or bus turn around time) is the most likely source of floating nodes.
While the insertion of null cycles eliminates the problem of bus contention, it creates the potential for floating nodes. For CMOS devices, null cycles are not a significant problem if the null period is relatively short because the load impedance on the bus is high enough that bus capacitance will hold the bus voltage at a valid logic level for several milliseconds. However, for circuits with stopped or slowed clocks or with low impedance loads, the node voltage may have time to drift to a critical voltage, V
crit
.
Accordingly, in both traditional busses and SoC busses, bus keepers (or bus holders) are often incorporated into the design. A bus keeper is a feedback circuit that prevents a node (e.g., a bit of a bus) from floating. The purpose of the bus keeper is to ensure that the bus bits are always driven to a valid logic level and, more particularly, to hold the immediately preceding driven logic level on the line.
The bus driver in the feedback circuit of a conventional bus keeper drives the bus, but with a weaker signal strength than the drivers of the data processing devices. Thus, the previously driven logic level is maintained during null cycles, but when the next data precessing device starts to drive the bus at the end of the null cycle, its strong driver easily overcomes the weak driver of the bus keeper.
These conventional bus keepers have several significant drawbacks. First, because they are essentially bus drivers, they still cause some bus contention, albeit not as bad as the contention between two strong drivers. Nevertheless, the contention causes excess power dissipation, and slower data transitions on the bus. Further, conventional bus keeper designs typically cannot easily be migrated between circuit designs because a conventional bus keeper must be designed with transistors specifically designed and scaled to provide the correct balance relative to the transistors of the strong drivers of the data precessing devices of the particular circuit.
Another well known tactic for preventing floating nodes is to incorporate pull up or pull down resistors on the bus bit lines. However, pull up and pull down resistors also present problems because the resistor values are difficult to guarantee, they waste power, they slow down bus operation, and they do not eliminate null cycles. Further, like bus keeper designs, they may be difficult to migrate the design to different processes and/or operating conditions.
SUMMARY OF THE INVENTION
The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a bus clock cycle, but rather observes and stores the value driven onto the bus during the first half of the clock cycle by one of the data processing drivers. Then, during the second half of the clock cycle, it drives the bus with the value stored during the first half of the bus cycle. Accordingly, a data processing device's driver drives the bus during the first half of the clock cycle without the need to overcome the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during t

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