Clock forward initialization and reset signaling technique

Details Clock forward initialization and reset signaling technique Clock forward initialization and reset signaling technique

2005-12-13

2005-12-13

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S375000, C713S400000, C713S501000, C713S502000, C713S503000, C713S600000, C375S371000, C375S373000, C375S376000, C327S156000, C327S160000, C327S162000

Reexamination Certificate

active

06976184

ABSTRACT:
A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

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