Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1993-09-03
2000-02-15
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326101, H03K 1900
Patent
active
060257407
ABSTRACT:
A clock feeding circuit for an integrated circuit includes logic circuit regions, a clock signal source, an input buffer connected to the source, and delay adjusting circuits. Each logic circuit region has a plurality of logic circuits, a buffer circuit for receiving the clock signal and providing it to the logic circuits, and interconnections wiring the logic circuits to the buffer circuit such that clock skew is minimized in the region. The adjusting circuits are disposed between the buffer and the respective logic circuit regions. Each adjusting circuit is composed of a plurality of delay elements, the number of which is pre-selected to determine the delay of the clock signal passing through it. A method for designing the integrated circuit includes (a) creating a schematic representation of the integrated circuit, (b) determining a layout and interconnections of each region, by which the clock skew in the regions is minimized among the logic circuits of each region, including simulating transmission of a clock signal from the clock source to each region to determine delays times of the clock signal from the clock source to the logic circuits; and (c) determining adjustments to the delay circuits which provide a minimum difference among time delays for the clock signal to reach one logic circuit in each region.
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OKI Electric Industry Co., Ltd.
Santamauro Jon
LandOfFree
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