Clock extractor for high speed, variable data rate communication

Details Clock extractor for high speed, variable data rate communication Clock extractor for high speed, variable data rate communication

1997-06-26

1999-10-05

Chan, Jason

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375327, H03D 324

Patent

active

059636084

ABSTRACT:
To derive a clock embedded in a digital data stream, a variable data rate synchronizer includes a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal, and a frequency estimator that derives an estimate of the frequency of the output of a voltage controlled oscillator. A phase lock loop includes a phase detector to which the digital data signal and the output of the voltage controlled oscillator are coupled and has an output coupled to a sweepable loop filter. The output of the loop filter is coupled to the voltage controlled oscillator. During an initital frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode, during which the sweep controller causes a sawtooth sweep of the loop filter, until the output of the loop filter corresponds to the actual frequency of said embedded clock signal, thereby locking the loop to the embedded clock.

REFERENCES:
patent: 4538119 (1985-08-01), Ashida
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 5367545 (1994-11-01), Yamashita et al.
patent: 5448598 (1995-09-01), Yousefi et al.

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