Clock extraction of a clock signal using rising and falling edge

Details Clock extraction of a clock signal using rising and falling edge Clock extraction of a clock signal using rising and falling edge

1995-09-08

1997-01-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375360, 375362, 327 2, 327 9, 327160, 327163, 370350, H03D 324

Patent

active

055984460

ABSTRACT:
A clock signal is extracted from a received signal. An edge detector detects edges of the received signal, where the received signal transitions between a logic 0 and a logic 1. A center between each pair of consecutive edges is determined. An extracted clock signal is generated. The phase of the extracted clock signal is varied based on the center between each pair of consecutive edges. For example, the center between each pair of consecutive edges is determined by counting a number of cycles of an over sampling signal which occurs between each pair of consecutive edges to obtain a bit width. The bit width is divided in half and the result added to an edge phase value to obtain a value for the center. Also, the phase of the extracted clock signal may be varied based on the center between each pair of consecutive edges as follows. An amount a plurality of centers varies from a center of the extracted clock signal is averaged to produce a phase error. In the preferred embodiment current center and an immediately previous center are used to produce the phase error. The phase of the extracted clock signal is changed an amount equal to the phase error.

REFERENCES:
European Telecommunication Standard (ETS) 300 175-2, European Telecommunications Standards Institute (ETSI), Reference DE/RES-3001-2, Oct. 1992, pp. 7,9,15,16,22 and 23.
European Telecommunication Standard (ETS) 300 175-3, European Telecommunications Standards Institute (ETSI), Reference DE/RES-3001-3, Oct. 1992, pp. 13,15,24,25,187,188.

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