Clock extraction circuit

Details Clock extraction circuit Clock extraction circuit

1998-03-13

2001-02-13

Chin, Stephen (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S214000, C375S317000, C375S355000, C375S361000, C327S175000, C369S124040

Reexamination Certificate

active

06188738

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a clock extraction circuit in the light receiver of a high-speed optical communication system. More particularly, the invention relates to a clock extraction circuit for extracting a clock signal, which furnishes the discrimination timing of a data signal, from the data signal.
2. Description of the Related Art
The light receiver of a high-speed optical communication system converts a data waveform, which has become distorted by distortion or noise produced by transmission, to a digital signal having a clean waveform. The light receiver performs so-called data and clock regeneration. When data is to be regenerated, the light receiver extracts and regenerates a clock signal from the received data signal and performs the regeneration of the data by a discriminator using the generation timing of the clock signal as a reference.
FIG. 12
is a block diagram showing the construction of a light receiver in an optical communication system. The light receiver includes a light-receiving element
1
for converting a light signal to an electric signal, an equalizing amplifier circuit
2
for equalizing and amplifying a 10-Gbps data signal, for example, output by the light-receiving element
1
, a timing extraction unit
3
for extracting a clock signal, which has a frequency the same as that of the bit rate, from the data signal that has been equalized and amplified, and a discriminator
4
for discriminating the data signal using the clock signal extracted from timing extraction unit
3
. In operation, a light signal that has arrived through an optical fiber is converted to an electric signal by the light-receiving element
1
. The electric signal is equalized and amplified by the equalizing amplifier circuit
2
. The timing extraction unit
3
extracts a clock signal CLK from the equalized waveform to trigger the discriminator
4
. The latter determines whether the equalized waveform is indicative of “0” or “1” at the sampling timing, thereby reproducing the original code pulses (data) and outputting the same. Since there is a change in delay time in regard to transmission through the transmission line, the discriminator
4
is triggered by a clock signal synchronized to the received data signal.
FIG. 13
is a block diagram showing the construction of the timing extraction unit
3
. The timing extraction unit includes a data edge detector
110
for detecting leading and trailing edges of the data signal, a bandpass filter (BPF)
111
, which has a center frequency identical with the bit rate of the data and a characteristic exhibiting a very high Q, generally on the order of 1000, and a limiter amplifier
112
for amplifying and shaping the waveform of the BPF output.
FIG. 14
is a diagram showing the f characteristic of the PF
111
, where f
0
represents the center frequency of the BPF and &Dgr;f the 3dB bandwidth of the BPF
111
. Accordingly, Q is given by the following:
Q=f
0
/&Dgr;f
  (1)
Though the circuits are not shown, the data edge detector
110
includes a branching circuit for branching the data signal in two directions, a delay circuit for delaying, by a prescribed length of time, one of the branched data signals, and an EX-OR (exclusive-OR) circuit for taking the exclusive-OR between the data signal and the output signal of the delay circuit to generate an edge signal having pulses at the leading and trailing edges of the data signal.
FIG. 15
is a waveform diagram showing the operation of the components in the timing extraction unit
3
. The data edge detector
110
generates pulses at the leading and trailing edges of the data signal, the bandpass filter
111
extracts the clock component, which has a frequency identical with the bit rate of the data, from the output of the data edge detector
110
, and the limiter amplifier
112
amplifies and shapes the waveform of the clock component.
If the duty cycle of the input data signal deviates from 100%, the output of the BPF takes on a small value. As shown in
FIG. 16
, duty cycle is the ratio of the duration T
H
of the high (H) level at 50% amplitude to the duration T of one time slot and is represented by the following equation:
 duty cycle=(
T
H
/T
)·100(%)  (2)
FIG. 17
is a waveform diagram showing the operation of the components in the timing extraction unit in a case where the duty cycle of the input signal has deviated from 100%. Here the BPF output takes on a small value and so does the output of the limiter amplifier, as a result of which the clock component decreases. More specifically, when duty cycle decreases, the positions of the detection pulses at the leading edges of the data are delayed and the positions of the detection pulses at the trailing edges of the data are advanced. The clock component is extracted following the combination of these pulses. Though the phase of the extracted clock component does not change, a portion that is canceled out occurs. The extracted clock component decreases for this reason.
The relationship between output amplitude Vout of the BPF and a phase shift &thgr; conforming to the duty cycle of the input data is given by the following equation:
Vout
=cos&thgr;×sin&ohgr;
t
  (3)
where we have
&ohgr;=2&pgr;f
0
&thgr;=&pgr;×&Dgr;t/T
and &Dgr;t represents the temporal deviation of the edges due to the fluctuation in duty cycle and T denotes one time slot (=1/f
0
). Equation (3) indicates that when the duty cycle of the input waveform is 100% (&thgr;=0), Vout attains its maximum value. Regardless of whether duty cycle increases or decreases, Vout decreases and Vout=0 is established at a duty cycle of 100±50(%) (&thgr;=±&pgr;/2).
FIG. 18
is a graph showing the relationship between the input waveform duty cycle and the BPF output amplitude based upon Equation (3).
When the bit rate is greater than several gigabits per second (Gbps) and the transmission distance is several dozen to several hundred kilometers in optical digital communication, a fluctuation in duty cycle waveform occurs owing to a fluctuation in optical wavelength at the leading and trailing edges, as illustrated in FIG.
19
. In
FIG. 19
, (1) illustrates the transmission waveform in a case where duty cycle has increased beyond 100%, and (2) illustrates the transmission waveform in a case where duty cycle has decreased below 100%.
Thus, since a waveform having fluctuating duty cycle enters the light receiver, the amplitude of the clock signal from the bandpass filter in the timing extraction unit decreases (i.e., the clock component decreases) and the quality of the clock declines, resulting in an increase in jitter and missing clock pulses. This means that the data cannot be reproduced correctly in the discriminator.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to so arrange it that even if a data waveform having fluctuating duty cycle is applied as an input, a clock signal having excellent quality can be extracted by improving duty cycle.
Another object of the present invention is to so arrange it that data can be reproduced correctly by preventing degradation of clock quality.
In accordance with the present invention, the foregoing objects are attained by providing a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal comprising a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data, wherein the data signal is input to the timing extraction unit via the filter. By thus providing a filter whose upper limited frequency is sufficiently lower than the bit rate of the data, duty cycle is improved when the data is input to the filter. As a result, a clock signal exhibiting excellent quality is obtained from the timing extraction un

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