Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-01-10
2003-06-10
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C327S101000, C327S102000, C327S175000
Reexamination Certificate
active
06578154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of precision-controlled duty cycle clock circuits for use with electronic devices. More specifically, the invention provides a circuit having an adaptive adjustment to improve the controllability of the duty cycle of an output clock signal in response to the changing characteristics of an input clock signal. The invention finds application in a variety of electronic devices, including wireless communications devices.
2. Description of the Related Art
Many high performance clocked digital circuits require a clock signal with a precisely controlled duty cycle. These types of circuits may use both the high and low phases of the clock signal to perform computations. If, for example, a circuit has the same timing requirements for both the high and low phase of the clock signal, then a clock signal with an accurate 50/50 duty cycle yields the maximum amount of time in each phase of the clock signal for any given frequency. Clock sources with less accurate control over their duty cycle would have to operate at a lower frequency to meet the timing requirements of such a circuit. Hence, clock circuits providing accurate duty cycle control allow either a higher clock rate or a lower core voltage, while still maintaining adequate timing margin for circuits operating from both phases of the clock signal.
SUMMARY OF THE INVENTION
A clock signal duty cycle control circuit is provided that receives an incoming signal from a clock signal input source and generates an improved output clock signal having an accurately controlled duty cycle. The circuit controls the duty cycle of the output clock signal by comparing the incoming signal to a reference value with a comparator. The reference value is derived from a reference charge stored on a capacitor. The reference charge is built up in the capacitor using the currents from a current source and a current sink, which are controlled using translated output signals from the comparator.
The duty cycle may be controlled by a reference value generated by building up of charge on a capacitor with a reference current. The charge, which is based on the reference current produced by combining currents flowing from a current sink and current source, produces a voltage across the capacitor. The current source and sink include devices that are programmed during a precharge mode of operation. During programming, the devices memorize a predetermined solution such that during a normal mode of operation the source current is identical to the sink current.
The invention is described in more detail below in terms of a preferred embodiment. As will be appreciated, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description of the preferred embodiments are to be regarded as illustrative in nature and not restrictive.
REFERENCES:
patent: 5210755 (1993-05-01), Nagler et al.
patent: 5485126 (1996-01-01), Gersbach et al.
patent: 5508664 (1996-04-01), Rizzo
patent: 5572158 (1996-11-01), Lee et al.
patent: 6121805 (2000-09-01), Thamsirianunt et al.
Fergusson Andrew
Madter Richard
Wynen John
Connolly Mark
Jones Day
Lee Thomas
Meyer, Esq. Charles B.
Pathiyal, Esq. Krishna K.
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