Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-08-12
2001-08-28
Cangialosi, Salvatore (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S516000, C375S376000
Reexamination Certificate
active
06282210
ABSTRACT:
BACKGROUND OF THE INVENTION
Dual In Line Memory Modules (DIMM) specifications define a modular memory device comprising small Printed Wiring Boards (PWB) boards with an array of memory devices. DIMM achieve high-speed data transfer rates of up to 100 Mhz in part by using an architecture that synchronizes the output data from the DIMM to a system clock. DIMMS with Synchronous Dynamic Random Addressable Memory (SDRAM) utilize clock signals provided to each DIMM for synchronization. DIMM modules with SDRAM having bus transfer rates of 66 MHz and above typically require about 1 ns worst case clock skew between the clock to the DIMM and clock to the SDRAM. DIMM modules commonly use a phase-lock-loop (PLL) circuit on each DIMM to re-drive the clock signals to both the memory devices and registers to minimize system clock loading and to provide low skew between input and output clock signals.
Timing error resulting from clock to data skew becomes an increasingly significant factor as memory device speed and bus transfer rates increase. Microprocessor system boards commonly have sockets for two to eight DIMMs and provide a duplicate copy of a single reference clock signal to each DIMM. Typically, the DIMM share a common bidirectional data bus resulting in each DIMM having a different data signal propagation time. Each inch of signal trace typically has more than 1 ns of signal propagation time, and sockets add additional capacitance and inductance that increase the skew in data propagation times between each DIMM.
Allowable timing error margins are reduced as bus transfer rates are increased. When worst case error margins are exceeded, reliability in mass production decreases. Timing problems show up as sporadic system crashes in some systems, which is unacceptable in systems such as servers that require consistent high reliability. DIMM specifications define a board outline and a system interface to provide for interchangeability between DIMMs having different memory device types and manufactures. Different types of DIMNs will have different AC characteristics, such as the data pin input capacitance and characteristic transmission line impedance that when combined with the variations in the AC characteristics of microprocessor systems boards result in worst case error margins being exceeded when minimum and maximum specifications and electrical characteristics of connectors are considered. Error margins are further reduced when the effects of temperature variations are taken into consideration. Device speeds vary with temperature. Memory systems are becoming increasingly more dependent on precision trace propagation times. Temperature swings of 0° C. to 70° C. results in 10% to 20% change in signal propagation times.
DIMM specifications allow the CAS latency to be varied on read cycles to provide additional clock periods to increase the read cycle time to SDRAM, however, the additional cycles typically results in microprocessor wait states that will degrade system performance. DIMM specifications do not provide flexibility in the number of clock periods in a write memory cycle. For DIMMs having long data propagation paths, a delayed clock signal to the individual SDRAM is needed that will allow additional set up time for the data signal to propagate and settle prior to being sampled; however, a delayed clock will increase the time for the data from the SDRAM on read cycles to reach the microprocessor or, alternately, be latched by a register on the system board requiring increased number of read clock periods to complete the memory read cycles. Phase-lock-loop clock drivers are available that provide selectable phase-offset magnitudes, but the prior art phase-lock-loop drivers do not allow for the phase-offset to be changed instantaneously (within a single clock period) in response to external stimuli. New methods are needed for providing precise and instantaneous phase-offset adjustment of the clock signal to each SDRAM based on the type of bus cycle in progress.
SUMMARY OF THE INVENTION
A clock driver of the present invention provides the flexibility to select, for desired clock periods, the magnitude of the phase-offset of an input clock signal in relationship to an output clock signal for increased reliability or optimal performance. A DIMM module of the present invention receives a system clock signal, has a synchronous memory device SDRAM that receives a local clock signal that is derived from the system clock signal. The local clock signal has a first desired phase-offset, for write cycles, and a second desired phase-offset for read cycles. A memory subsystem of the present invention has a bus master device that is clocked by a system clock signal and a slave memory device that is clocked by a local clock signal. The local clock signal has, for read cycles, a first desired phase-offset in relationship to the system clock signal and, for write cycles, a second desired phase-offset for read cycles.
Preferred embodiments are described herein for a clock driver of the present invention that has a zero-delay loop circuit that generates a reference signal from an input clock signal that is routed through a multiplexer to an output clock signal. A feedback signal is provided to the zero-lock-loop circuit to determine the phase-offset of the reference signal; the zero-lock-loop circuit adjusts the phase-offset of the reference signal until the feedback signal is in-phase with the input clock signal. The feedback signal is a delayed version of the reference signal, where the delay is selected to approximate the cumulative delays of the reference signal through the multiplexer, to the output clock signal, and through the external trace connecting the output signal to an external device, such that when the feedback signal is in-phase with the input clock signal, the signal received by the external device is in-phase with the input clock signal. The multiplexer receives one or more offset signals that are each a delayed version of the reference signal such that each offset signal is staggered in time from one another and the reference signal. A state machine determines which signal received by the multiplexer is routed to the output signal providing flexibility to select the phase-offset of the output signal in relationship to the input signal for select cycles or half cycles.
Alternate embodiments provide self calibration function where some internal delay paths are self-adjusted by the clock driver circuit when the clock driver circuit enters a calibration mode. Gates having low propagation times are selectively closed while select signals are routed to phase-comparator circuits that provide a signal that alters specific delay paths. The calibration function is typically triggered by a software command after a warm-up delay.
The preferred embodiments described herein are designed to provide a local clock signal to an array of synchronous memory devices on a DIMM module having an interface to a bus master device provided by an address bus, a data bus, and a control bus. The state machine tracks the control bus, detects read cycles and write cycles to the DIMM, and selects a first phase-offset for read cycles and a second phase-offset for write cycles. Alternate embodiments provide for the magnitude of phase-offset for read and write signals to be programmed by software providing software programs the flexibility to select the optimal delays by trial and error.
Alternate embodiments provide for three phase-offset set options: a first that is selected for read cycles, a second that is selected for write cycles, and a third that is selected during the transition clock period between two clock periods having different phase-offset, the third phase-offset has a magnitude that is in between the magnitude of the first phase-offset and the magnitude of the second phase-offset, such that the duty cycle of the transition clock period approximates a 50% duty cycle.
A preferred embodiment utilizes a phase-lock-loop circuit that provides an output clock that has a fixed phase-offset from an input cl
Buchle Jeff
Rapport Russell
Cangialosi Salvatore
Denko J. Scott
George + Donaldson LLP
Staktek Group L.P.
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