Clock domain crossing FIFO

Details Clock domain crossing FIFO Clock domain crossing FIFO

2007-03-06

2007-03-06

Corrielus, Jean B. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C711S100000, C710S004000, C710S052000

Reexamination Certificate

active

09999007

ABSTRACT:
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock.

REFERENCES:
patent: 5452434 (1995-09-01), MacDonald
patent: 6209053 (2001-03-01), Kurts
patent: 6370600 (2002-04-01), Hughes et al.

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