Clock distribution network with modular buffers

Details Clock distribution network with modular buffers Clock distribution network with modular buffers

1996-05-01

1999-03-09

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 82, 327144, H03K 1900

Patent

active

058806075

ABSTRACT:
A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a buffer block containing one or more nth-level buffers implemented with predefined modular buffers. The logic block includes one or more predefined areas containing clocked logic elements. The number of clocked logic elements in a predefined area is constrained to be less than or equal to a predetermined maximum number. Each nth-level buffer receives the clock signal outputted by the external buffer and distributes this clock signal to the clocked logic elements within a corresponding predefined area of the logic block. The nth-level buffer driving each predefined area is implemented by selecting one or more buffers from a family of predefined modular buffers appropriate for the number of clocked logic elements in the predefined area. In cases where more than one predefined modular buffer is selected, the selected predefined modular buffers are connected in parallel. Because a family of predefined modular buffers is used instead of custom buffers, the design of the buffer block is greatly simplified. Moreover, this network is easily implemented with an automated place and route design tool by predefining each modular buffer in a standard cell library of the automated place and route design tool.

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