Clock distribution network with dual wire routing

Details Clock distribution network with dual wire routing Clock distribution network with dual wire routing

1997-06-16

1999-11-30

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326101, H03K 1900

Patent

active

059949244

ABSTRACT:
A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the tapping point near the circuit component. Clock signals from the two wires are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.

REFERENCES:
patent: 5896055 (1999-04-01), Toyonaga et al.

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