Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1999-07-06
2000-11-07
Nguyen, Tan T.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326101, H03K 1900
Patent
active
061442240
ABSTRACT:
A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the next routing segment. The next routing segment routes clock signals to the tapping point near the circuit component by two emanated wires from the previous routing segment. Clock signals from the routing segments are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.
REFERENCES:
patent: 5391942 (1995-02-01), El-Ayat et al.
patent: 5416918 (1995-05-01), Gleason et al.
patent: 5471157 (1995-11-01), McClure
patent: 5570045 (1996-10-01), Erdal et al.
patent: 5656963 (1997-08-01), Masleid et al.
patent: 5668484 (1997-09-01), Nomura
patent: 5732249 (1998-03-01), Masuda et al.
patent: 5923188 (1999-07-01), Kametani et al.
patent: 5994924 (1999-11-01), Lee et al.
Lee Jin-Fuw
Ostapko Daniel Lawrence
International Business Machines - Corporation
Nguyen Tan T.
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