Clock distribution network planning and method therefor

Details Clock distribution network planning and method therefor Clock distribution network planning and method therefor

1998-06-18

2001-10-16

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C002S006300, C002S007000, C002S010000

Reexamination Certificate

active

06305001

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to clock distribution network planning for ASICs, and in particular, to methods and computer-aided design tools for planning the clock distribution network in the conceptual design phase of the ASIC devices to reduce clock skew, ground bounce, VDD noise and idle clock cycle time.
2. Description of the Related Art
The routing and distribution of the clock to elements of an integrated circuit, or more specifically, an application specific integrated circuit (ASIC), is an important factor to consider in the design of ASICs. To take an analogy, for instance, the clock of an ASIC may be seen as the heart and blood flow of a human body, whereas the clock routing and distribution of an ASIC may be seen as the arteries and veins of a human body. Just like the human body requires that the arteries and veins be properly distributed in order for each organ to function properly and together with other organs, the clock routing and distribution of an ASIC should be designed so that the clock-receiving elements function properly and together so that the intended functions of the ASIC are achieved. One of the intended functions of clock recipient elements of an ASIC, for example, is to propagate data to an intended functional destination of an ASIC.
Referring to
FIG. 1
, a simple prior art chain of D-type flip-flops
20
is shown, wherein the D flip-flops (D
0
-Dn) are shown sequentially cascaded together to propagate data from a data input to a data output. As it is conventionally known of these types of data-propagating chains of D-type flip-flops, the Q-output of one of the flip-flops in the chain is coupled to the D-input, of the next flip-flop in the chain in the direction in which data propagates. Thus, in the example shown in
FIG. 1
, the Q-output of flip-flop D
0
is coupled to the D-input of flip-flop D
1
; the Q-output of flip-flop D
1
is coupled to the D-input of flip-flop D
2
; and so on. The chain of D flip-flops are driven by a common clock source
22
by way of a clock distribution network
24
. In the example shown in
FIG. 1
, the clock distribution network
24
includes an input for the clock source
22
situated near the flip-flip D
0
, and extends therefrom parallel with the flip-flops in the direction of data propagation, and includes a branch to each of the clock inputs of the flip-flops in the chain
20
.
In operation, a clock pulse or triggering edge of the clock causes each of the D flip-flops in the chain
20
to propagate data from its D-input to its Q-output. Each consecutive clock pulse or triggering edge causes the data to move further down the chain of flip-flops. In the example shown in
FIG. 1
, per every clock pulse or triggering edge, data at the D-inputs of flip-flops D
0
-Dn propagates to the Q-outputs of the flip-flops D
0
-Dn, respectively. If there are no delays between the Q-outputs and the D-inputs of consecutive flip-flops in the chain
20
, then per every clock pulse or triggering edge, data at the D-inputs of the flip-flops propagates to the D-inputs of the next flip-flops in the chain
20
. It is desired that the clock pulse or triggering edge of the clock occur at the same time (or are in-phase) at the inputs of all the flip-flops, in order for the data as a whole to propagate together down the chain
20
.
The problem with the data propagating chain
20
is that with the clock distribution network
24
shown in
FIG. 1
, the triggering edge or pulse of the clock does not reach all the clock inputs of the flip-flops at the same time. This results in the data not properly propagating as a whole through the chain; a condition generally termed in the art as “clock skew.” To illustrate the problem of clock skew, assume that the time delay for data to propagate from the Q-output of a flip-flop to the D-input of the next flip-flop in the chain is given by &Dgr;T
D
. Also, for this example, because the clock distribution network
24
shown in
FIG. 1
requires the clock to propagate a longer length to reach the clock inputs of the flip-flops down the chain
20
, assume that the time difference of clock at the clock inputs of consecutive flip-flops is given by &Dgr;T
C
.
Given the above assumptions for the example, if the time delay &Dgr;T
D
for the data to propagate from the Q-output of flip-flop D
0
to the D-input of flip-flop D
1
is more than the time difference &Dgr;T
C
of the clock at the clock inputs of such flip-flops, then triggering edge of the clock it the clock input of flip-flop D
1
will clock the current data at its D-input to its Q-output before the next data (the data that propagated through flip-flop D
0
) propagates to the D-input of flip-flop D
1
. This is the desired result, that the next data does not propagate to the D-input of the next flip-flop before that flip-flop is clocked for the current data.
However, with the clock distribution network
24
shown in
FIG. 1
, problems occur for flip-flops down the chain
20
. For instance, the time delay of the clock to reach the clock input of flip-flop D
2
is given by 2&Dgr;T
D
. Assume now that the time delay &Dgr;T
D
is smaller than the time delay 2&Dgr;T
C
, then the data that propagated through flip-flop D
1
will reach the data input of flip-flop D
2
before it is clocked. Thus, instead of the current data propagating through flip-flop D
2
for that triggering time, the next data propagates through flip-flop D
2
, thereby, losing the current data for flip-flop D
2
. This results in the data as a whole improperly propagating down the chain
20
. Thus, it is desirable that the clock distribution network be designed so that the flip-flops, or more generally, the clock recipient elements be clocked at substantially the same time to reduce or eliminate the effects of clock skew.
Referring now to
FIG. 2
, a block diagram of a prior art clock distribution network
30
formed on an ASIC substrate
37
is shown that reduces or eliminates the problem of clock skew. The prior art clock distribution network
30
reduces the clock skew problem by attempting to cause the phase of the clock signal at the clock inputs of all the clock recipient elements in the ASIC to be substantially the same. The clock distribution network
30
is generally referred in the relevant art as a “balanced clock tree,” and therefore, will be referred to as such hereinafter.
The balanced clock tree
30
shown in
FIG. 2
includes a main buffer
32
for receiving a clock signal from a clock source
34
, and used as an initial driving stage for supplying the clock signal to the clock recipients of the ASIC. The output of the main buffer
32
is coupled to an H-shaped conductive tree structure
36
that is used as an initial conduit for the clock to propagate through to reach the clock recipients. The H-shaped conductive tree structure
36
includes an initial entry wide conductive line
38
(or entry conductive line, for short) having a first end coupled to the output of the main buffer
32
and a second opposite end connected to the middle of the mid-section conductive branch
40
of H-tree conductive structure. The ends of the mid-section conductive branch
40
connect to the middle of the outer conductive branches
42
and
44
of the H-tree conductive structure
36
. Each of the ends of the outer conductive branches
42
and
44
is coupled to a buffer tree-network
46
, which is, in turn, coupled to the clock recipients
48
.
The H-tree conductive structure
36
including the entry conductive line
38
are designed so that the phase of the clock signal as it is split by the H-tree structure are substantially the same at the ends of the outer conductive branches
42
and
44
, or alternatively, at the points in which the buffer tree-networks
48
connect to the H-tree structure. This is accomplished by forming the H-tree structure
36
on a substrate
37
that has substantially uniform dielectric constant, and by having the same conductive line lengths from the output of the main buffer
32
to the ends of the outer conduc

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