Clock distribution for interconnect structures

Details Clock distribution for interconnect structures Clock distribution for interconnect structures

2005-03-31

2008-09-16

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

Loading initialization program

C713S001000, C713S100000, C713S400000, C713S500000

Reexamination Certificate

active

07426632

ABSTRACT:
Some embodiments of the invention include an interconnect structure having a plurality of connector circuits to transfer messages among a number of devices. Each of the connector circuits includes a data transfer unit to transfer messages and a clock unit to provide timing to transfer the messages. The interconnect structure propagates a master clock signal serially through the clock units of the connector circuits to generate a number of different input clock signals. The timing provided by each of the clock units is based on the timing of one of the input clock signals. Other embodiments are described and claimed.

REFERENCES:
patent: 4866606 (1989-09-01), Kopetz
patent: 6377077 (2002-04-01), Shiraishi
patent: 6477659 (2002-11-01), Ho
patent: 6963989 (2005-11-01), Cullum et al.
patent: 2002/0083255 (2002-06-01), Greeff et al.
patent: 2006/0221984 (2006-10-01), Denham
patent: 1402140 (2003-03-01), None
“Office Action—Chinese Application No. 200610084165.7”, 21 pgs.

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