Clock distribution circuit and layout design method using same

Details Clock distribution circuit and layout design method using same Clock distribution circuit and layout design method using same

2011-08-02

2011-08-02

Chang, Daniel D (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S112000, C327S237000

Reexamination Certificate

active

07990179

ABSTRACT:
A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit.

REFERENCES:
patent: 7191418 (2007-03-01), Lee et al.
patent: 2007/0033560 (2007-02-01), Johnston
patent: 2002-269166 (2002-09-01), None

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