Clock distribution circuit

Details Clock distribution circuit Clock distribution circuit

1999-12-28

2002-04-23

Bulter, Dennis M. (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000

Reexamination Certificate

active

06378080

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock distribution circuit for use in semiconductor integrated circuits and the like, and more particularly to a clock distribution circuit with reduced clock skew.
2. Description of the Related Art
Recently, large-scale integrated circuits (LSIs) have increased rapidly in clock frequency, and the fastest ones have reached a frequency as high as 1 GHz. An increase in clock frequency can immediately improve the performance of LSIs since clock synchronous circuits are the most common in LSI design at present. Thus, increasing clock frequency is a technique of great significance. LSIs in use for conventional computers and the like have various configurations which have been proposed for distributing a clock to clock reference terminals with reduced phase differences thereamong. Those in common use are, for example, clock distribution circuits of tree structure and clock distribution circuits of mesh type. Clock distribution circuits of tree structure are described in Japanese Patent Application Laid-Open Nos. Hei 5-233092 and Hei 9-307069. Clock distribution circuits of mesh type are disclosed in Japanese Patent Application Laid-Open No. Hei 6-244282.
FIG. 1
is a circuit diagram showing a conventional clock distribution circuit of tree structure. The conventional tree-structured clock distribution circuit has an LSI chip
702
provided with an input terminal
701
through which a clock signal is input. The input terminal
701
is connected with inverters
703
through
705
in series. The inverter
705
in turn is connected with clock distribution wirings
712
L and
712
R having the same length and the same width. The clock distribution wiring
712
R is connected with inverters
706
a
and
706
b
at its end. The clock distribution wiring
712
L is connected with inverters
706
c
and
706
d
at its end. The inverters
706
a
-
706
d
in turn are provided with wirings having the same length and the same width, being connected with a plurality of inverters
707
a
and
708
a
-
708
d
, inverters
707
b
and
710
a
-
710
d
, inverters
707
c
and
709
a
-
709
d
, and inverters
707
d
and
711
a
-
711
d
, respectively.
In the conventional clock distribution circuit configured thus, each wiring is formed in the same length and the same width which reduces the clock skew of the clocks arriving at the ends. A plurality of isometric wirings are also used from the buffers at the ends of the tree to a plurality of terminals for clock reference to reduce the clock skew. The clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 5-233092 mentioned above is of such configuration.
Meanwhile, the conventional clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 9-307069 mentioned above includes delay buffers to adjust the wiring delay at each node of the clock tree. Such configuration puts each stage of the clock tree into the same phase.
FIG. 2
is a circuit diagram showing a conventional clock distribution circuit of mesh type. The conventional mesh-type clock distribution circuit has an LSI chip
802
which is defined into a plurality of blocks
801
. Each of the blocks
801
contains wirings
806
in the form of cross-meshes. The chip
802
is further provided with a buffer
804
for distributing a clock signal to the plurality of blocks
801
as a clock driver. In addition, clock distribution wirings
803
having the same length and the same width are provided from the buffer
804
to each of the blocks
801
.
In the conventional clock distribution circuit configured thus, the use of mesh-form wirings produces smaller wiring resistances since the resistances can be regarded as parallel resistances. This allows the clock signals on lattice points to vary in voltage with a timing difference as small as negligible. The clock distribution circuit described in Japanese Patent Application Laid-Open No. Hei 6-244282 mentioned above is of such configuration.
Other types of clock distribution circuits include those described in Japanese Patent Application Laid-Open No. Hei 6-282350, which have LSIs containing a plurality of intra-block distribution circuits that utilize phase locked loops (PLLs), delay locked loops (DLLs), or the like having variable delay adjusters and phase comparators.
In the conventional clock distribution circuit described in the publication, the PLLS, DLLS, or the like always make comparisons and adjustments on mutual phases, so as to supply clocks in phase through clock reference terminals. According to this circuit, clocks can be distributed to the ends in phase even in the cases where the clock distribution wirings differ from each other in capacitance.
There have also been disclosed clock distribution circuits in which frequency multipliers using a variable delay adjuster are placed on the node portions of the clock tree (Japanese Patent Application Laid-Open No. Hei 7-253825). In the conventional clock distribution circuits, an external clock is multiplied inside to produce a higher clock.
These clock distribution circuits have been designed on the assumption that each clock wiring has a resistance component and a capacitance component. In this connection, a clock distribution circuit designed should be verified whether or not it satisfies the allowable value of clock skew, using a circuit modeling technique in which the rising time of a clock is obtained from the product of the load capacitance and the resistance component of the wiring. If the allowable value is satisfied, then the design is realized into circuitry.
“IBM Journal of Research and Development vol. 39, No.5” 9 (1995), pp.547-566, describes, however, the following points on microprocessors operating at a frequency of 300 MHz. That is, for a 1-cm-length wiring, the propagation delay time of the wiring is 130 through 370 pico-seconds; the rising time of propagated signals ranges from 100 to 900 pico-seconds; and the propagation delay time is not negligible with respect to the rising and falling times of the signals. It also reads that under these circumstances wirings must not be considered as RC distributed constant circuits in consideration of capacitance components and resistance components alone, but as transmission lines which further takes inductance into account.
Meantime, the clock distribution circuits described in the above-cited publications were designed in terms of RC distributed constant circuits. This produces a problem with high-frequency operations.
For example, the conventional clock distribution circuits described in Japanese Patent Application Laid-Open Nos. Hei 5-233092 and Hei 6-244282 are all under the assumption that the propagation characteristics of signals will be determined only by resistance components and capacitance components. This precludes the proper operation of the circuits on the condition that the rising time of the clock approaches the signal propagation time of the signal lines and that their inductance components are not negligible. In the cases where the rising time of the clock is e.g. 10% the clock frequency, inductance becomes not negligible at frequencies above 300 MHz since the propagation time of the signal lines is in the range of 130 and 370 pico-seconds for each 1-cm wiring.
Moreover, the circuits described in Japanese Patent Application Laid-Open No. Hei 6-282350 with PLLs, DLLs or the like using variable delay adjusters and phase comparators become extremely hard to construct at frequencies e.g. above 1 GHz. For example, “IEEE International Solid-State Circuits Conference” 2 (1997), pp.330-331, describes a technique in which a PLL itself has a jitter of 154 pico-seconds. When the PLL is mounted on an LSI, the jitter even increases because of uncertain factors such as source noise. The aforesaid literature, pp.332-333, describes another technique in which a DLL itself has a jitter as small as 68 pico-seconds; however, the jitter increases up to 400 pico-seconds when source noise of 1 MHz is applied. As se

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